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Found 3 results

  1. Hi, I have an issue where teh DUT returns an X for register read but the reg2bus still sees it as a 0. When I was going over the uvm_reg_bus_op struct the type for data is uvm_reg_data_t which is only 2-state. Is there a way to override this argument to support 3/4-state? Maybe uvm_reg_data_logic_t? Please let me know. Thanks in advance! Vignesh
  2. Hello Folks, I am unable to get a response from the vsequencer to my register model sequence. I see that the register model sequence does generate the first transaction and when the response of this transaction comes back to the vsequencer the sequence hangs. I found on couple of forums that setting provides_responses bit to 1 in the adapter class should resolve this issue. However I am still not able to make this work. Here are the steps that I followed to Integrate uvm_reg model in my uvm environment. 1. Generate the uvm_reg model using one iregGen/ralGen script 2. Instanti
  3. I am working on a design that supports single, or bursting access to a memory. I would like to keep the abstraction of the register model (ie. MEM.Write(), MEM.bust_write()...). It appears that the register model breaks up the burst-ed writes into single transactions. What is the best way to implement a burst_write (Basically one address, and many data items) into a single seq_item for the driver to implement?
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