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  1. SA... the following lines are extracted from UVM user manual : class get_consumer extends uvm_component; uvm_blocking_get_port #(simple_trans) get_port; // the first line is understood to be class declaration as extension from uvm_component class. // I can't understand the 2nd line ,, could anyone here help me ?
  2. Hi, I'm using IUS 12.20.004 and trying to probe the UVM hierarchy for post processing in Simvision. Is it possible to probe variables of a task or function which is inside a class? I followed this guide: http://www.cadence.com/rl/resources/white_papers/post_process_uvm_wp.pdf I'm able to see data members of a class (the test class for example), but if there's a task or function inside the class, it isn't probed so I can't see its variables in the waves. Thanks, Eli
  3. Hi Guys, I am using UVM Register model to mimmick RTL's register implementation. Some registers are not implemented in RTL which are going to be connected to output port of some other module. I have got a HDL path of register as an output port declaration of some module. Something like: The HDL path is: "tb_top.dut_u.interrupt_module_u.o_ext_interrupt" o_ext_interrupt is declared as output port inside interrupt_module, which is not connected to any other wire or register. Can this output port's value be changed by writing to it via UVM BACKDOOR ? I am using following API: register_name.write(status,data,UVM_BACKDOOR,default_map); I dont see any change in value in the register. I think it is happening because the destination (o_ext_interrupt) is output of the module. I am using Cadence's simulator: irun. Please help if anyone is aware of such issue. Regards, Vismay.
  4. Hi, I have a interface monitor where i am capturing data from the interface. I need to pass valid data captured from the interface to the scoreboard for comparison. But the behaviour of interface signals and the way they are asserted depends on the register configuration. Now this config info is not known to the interface or the interface monitor. So while implementing the monitor, should i define two monitors 1) interface monitor which just samples all the data from the bus. 2) process data got in 1) furthur depending on the register config & then pass it on the scoreboard for comparison. Also should this be done using analysis ports? I think this is the right way but wanted to know if there is anything that UVM recommends in such cases. Thanks in advance. Parag
  5. In my earlier UVM days I ran into this confusing error message a number of times. I just hit it again, so am posting my solution here, to share and to help myself rediscover when it is time. Error (running IUS 13.1): uvm_analysis_imp_my_snoop #( xyz_trans, my_scoreboard) my_snoop_port; | ncvlog: *E,EXPENC (/user/goblin_dev/tb/my_scoreboard.svh,60|50): Expecting the keyword 'endclass'. Below is the pseudo code w/o the error. In converting the real code to pseudo code (to make it more succinct and sterilized), I do not believe I created any inconsistencies, but this is not what was compiled, of course. `uvm_analysis_imp_decl(_my_snoop) class my_scoreboard extends uvm_scoreboard; `uvm_component_utils(my_scoreboard) uvm_analysis_imp_my_snoop #( xyz_trans, my_scoreboard) my_snoop_port; function void build_phase(uvm_phase phase) my_snoop_port = new("my_snoop_port",this); endfunction : build_phase function void write_my_snoop( xyz_trans t ); //guts here endfunction : write_my_snoop endclass : my_scoreboard The error occurred when the following line was missing from above. `uvm_analysis_imp_decl(_my_snoop) So, without this macro called, the uvm_analysis_imp_my_snoop class is not declared. So, I would think that the error message would instead say that the class was not found. (I should try removing some random class that my tb needs and see what error message appears - b/c that is the error message I would expect here as well.) Appendix: The following code is taken from uvm-1.1/uvm_lib/uvm_sv/src/macros/uvm_tlm_defines.svh : // MACRO: `uvm_analysis_imp_decl // //| `uvm_analysis_imp_decl(SFX) // // Define the class uvm_analysis_impSFX for providing an analysis // implementation. ~SFX~ is the suffix for the new class type. The analysis // implemenation is the write function. The `uvm_analysis_imp_decl allows // for a scoreboard (or other analysis component) to support input from many // places. For example: // //| `uvm_analysis_imp_decl(_ingress) //| `uvm_analysis_imp_decl(_egress) //| //| class myscoreboard extends uvm_component; //| uvm_analysis_imp_ingress#(mydata, myscoreboard) ingress; //| uvm_analysis_imp_egress#(mydata, myscoreboard) egress; //| mydata ingress_list[$]; //| ... //| //| function new(string name, uvm_component parent); //| super.new(name,parent); //| ingress = new("ingress", this); //| egress = new("egress", this); //| endfunction //| //| function void write_ingress(mydata t); //| ingress_list.push_back(t); //| endfunction //| //| function void write_egress(mydata t); //| find_match_in_ingress_list(t); //| endfunction //| //| function void find_match_in_ingress_list(mydata t); //| //implement scoreboarding for this particular dut //| ... //| endfunction //| endclass `define uvm_analysis_imp_decl(SFX) \ class uvm_analysis_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_ANALYSIS_MASK,`"uvm_analysis_imp``SFX`",IMP) \ function void write( input T t); \ m_imp.write``SFX( t); \ endfunction \ \ endclass
  6. I've run into the following issue using the built-in UVM register tests. The built-in UVM register tests (seem to) start R/W-ing immediately after top-level reset is released. This was fine, initially. See attached image "Capture". We now have some delay between the release of top-level reset and the actual reset going to the register block. This is resulting in a read occurring before reset to the rtl regblock is released, and causes the test to hang. See attached image "Capture2". Without modifying the built-in register tests/sequences, how would anyone suggest that we cleanly delay the stimulus? Perhaps I just need to make the stimulus aware of the different reset when the model/stimulus is generated, or simple add some delay to a phase before the R/W-ing starts. (The former sounds right. If that's the solution, I'll need to figure out how we're generating the model/stimulus.) I've just started hunting around for the built-in UVM register test sequences and will return to it tomorrow, but will anyone tip me off as to what names I should be searching for? thanks This has been useful, https://verificationacademy.com/cookbook/registers/builtinsequences, but it seems I need to do some more reading and hunting before I grasp how the built-in register stimulus is created and used.
  7. Not sure do you have similar problem? I have a problem in handling the reset value in RAL. f the reset value of a field in the register is don't care, what can I do for it? Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked. Do you guys think it is a feasible way? Thanks.
  8. One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad pun. ) =Adam Sherilog, Cadence
  9. Doulos will be running a webinar on Friday 26th April "The Finer Points of UVM Sequences". Presented by John Aynsley, Doulos CTO Register here! http://www.doulos.com/content/events/easierUVM_The_Finer_Points.php
  10. Hi I am new to UVM. Can any one provide the sample example for using uvm_post_main_phase? Thanks, Ravi
  11. Dear SystemVerilog/UVM User, I've setup a SystemVerilog Meetup in Silicon Valley for people who are interested in hashing over problems they're having or learning new features in a group setting. http://www.meetup.com/SystemVerilog-Social-Club-Silicon-Valley/ I look forward to seeing you there. all the best, Linc Jepson
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