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  1. Hi, I am using uvm_resource_db to set and get any component configuration. But I am getting an error saying configuration object is not found. Its something that its not able to get the config object from configuration space. In env build_phase, I do set the configuration as below: uvm_resource_db#(io_config)::set("io_agent_0*","io_agent_config",m_io_config,this); And in io_agent, below code is used to get the configuration: assert(uvm_resource_db#(io_config)::read_by_name(get_full_name(),"io_agent_config",cfg,this) else uvm_report_fatal("io_agent","not able to get the configuration object"); Kindly let me know if there is anything wrong in the above usage. And also, can I do setting configuration through uvm_resource_db and getting it through uvm_config_db. Thanks A.Sunitha
  2. a usual way to do it is to create a wrapper object and push the wrapper into config_db. Then get this wrapper object from config_db and assign it to the virtual interface pointer (not mentioning the details here) Creating the virtual interface container wrapper parameterized to the strongly typed interface helps here. but in the uvm component, a pointer needs to be created for the parameterised interface. If not wanting the classes to be parameterized, how the virtual interface handle can be created without specifying the parameter as either a default parameter in base class or override is necessary for creating handle?. The component will get the wrapper object from config_db and assign it (the virtual interface in the object) to the virtual interface pointer Thanks.
  3. Hi all, First I apologize if I am using the wrong forum for the question. Please, I would like to know whether someone here could give updates on uvm-sc status. When will a first public release be available ? Regards
  4. I am trying to run a couple of test cases using script.But I am getting an error message after running the first test case.This stops the simulation.I am attaching the LOG with this mail.I don't understand why this is happening. I checked previous posts and added +UVM_OBJECTION_TRACE in the vsim command.But I am not able to find out the cause of the error.Can anybody help me?? # UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top raised 1 objection(s): count=1 total=1 # UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object uvm_test_top): count=0 total=1 # AT TIME=0,APB MASTER IN RESET MODE # AT TIME=1200000,APB MASTER IN ACTIVE MODE # AT TIME=45400000,*************************** EXPECTED_DATA=1792474624,RECEIVED DATA=1792474624 # AT TIME=186600000,*************************** EXPECTED_DATA=222,RECEIVED DATA=222 # AT TIME=231800000,*************************** EXPECTED_DATA=1504340502,RECEIVED DATA=1504340502 # AT TIME=349000000,*************************** EXPECTED_DATA=2367782205,RECEIVED DATA=2367782205 # UVM_INFO Test_Cases/my_test.sv(40) @ 349000000: uvm_test_top [root objections] # The total objection count is 1 # --------------------------------------------------------- # Source Total # Count Count Object # --------------------------------------------------------- # 0 1 uvm_top # 1 1 uvm_test_top # --------------------------------------------------------- # # UVM_INFO Test_Cases/my_test.sv(43) @ 349000000: uvm_test_top [my_component objections] # The total objection count is 1 # --------------------------------------------------------- # Source Total # Count Count Object # --------------------------------------------------------- # 1 1 uvm_test_top # --------------------------------------------------------- # # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_test_top dropped 1 objection(s): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_test_top all_dropped 1 objection(s): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source object uvm_test_top): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source object uvm_test_top): count=0 total=0 # UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 349000000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase # # --- UVM Report Summary --- # # ** Report counts by severity # UVM_INFO : 12 # UVM_WARNING : 0 # UVM_ERROR : 0 # UVM_FATAL : 0 # ** Report counts by id # [OBJTN_TRC] 6 # [Questa UVM] 2 # [RNTST] 1 # [TEST_DONE] 1 # [my_component objections] 1 # [root objections] 1 # ** Note: $finish : C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430) # Time: 349 us Iteration: 68 Instance: /my_top # 1 # Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430 # Simulation Breakpoint: 1 # Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430 # MACRO ./run_do PAUSED at line 18
  5. Hi, I am diagnosed with ‘Wrist tendinitis’/’tenosynovitis’ due to RSI (Repetitive Strain Injury). Hence I started using speech recognition as much as possible. On windows, controls are 80% accurate and dictation is 50% accurate. With practice, I am trying to use keyboard and voice recognition just the same way a pianist would sing. I think with the wealth of research in speech recognition, it is possible to get a decent accuracy 1. for coding (UVM, systemverilog) as there are predefined set of keywords, classes, functions etc. 2. for GUI tool controls An example of coding: to see in editor "class myenv extends uvm_env;" I would Say: "class" type: myenv Say:"extends uvm_env;" For GUI usage, tool vendors/users could come up with a number of useful features similar to keyboard shortcuts. These features may be implemented both on Windows and Linux platforms. (Hope in few years engineers are able to dictate their code into a tool and debug it too! Also wish there is research on use of various HCIs for EDA) Thanks for reading my request! Regards, Kal Gandikota P.S.: I used windows speech recognition to write this e-mail as I am suffering from wrist pain. Please kindly ignore grammar mistakes.
  6. Hello all, How would one go about leveraging UVM for ES level DUT verification? Most of the stuff from RTL still applies but how do we correctly use the driver and monitor if the DUT does not have signals, but has TLM ports/sockets. The UVM states that one agent should be used per interface, but the problem on the ESL is that there are no signals so how do we monitor TLM ports/sockets with the monitor, while the driver stimulates the DUT? How do we connect ports/exports to the driver, monitor and the DUT simultaneously? A solution without using analysis ports would be great. I've included an image for easier reference. I guess that on ES level the monitor and driver are redundant, but then the sequencer would have to send packets to a checker and the DUT simultaneously, which would require either two ports or an analysis port. Another option would be to keep everything the same as in the image and have two ports, one from the driver to the DUT, and one from the driver to the monitor and send packets simultaneously. Please state your thoughts on this.
  7. Hi there A register can have different RTL implementation based on access_mode. ie., When a register REG_1 is read in backdoor, actual HDLPATH of the register would point to 'top.abc.dout'. When a register REG_1 is written in backdoor, actual HDLPATH of the register would point to 'top.abc.dout_temp' We want to program different hdlpaths to REG_1 based on access mode (READ or WRITE). Does UVM_REG provide ready-made hookups or methods like add_hdl_path_slice() methods to setup different hdlpaths to READ/WRITE backdoor access? (Inside the DPI based backdoor access itself?) I checked that write_backdoor and read_backdoor methods need to be overwritten to setup different HDLPATHs based on READ/WRITE access modes. But this involves overriding string based DPI backdoor access factory methods. I'm looking for an alternative here, if it really exists. Suggestions to this requirement, very much appreciated. Best regards Balasubramanian G
  8. Hi there We want to traverse through all registers present in a UVM_REG_BLOCK based on increasing address. We have the following pseudocode: model.NTB_DB.get_registers(total_regs_ntb); foreach (total_regs_ntb) begin total_regs_btb.write(status, wdata, .parent(this)); end But, the above source code does not go through the registers space based on address. ie., When I have a 2-dimensional array of registers, array indices are chosen first(not addresses). Any help to workaround this problem is appreciated. Best regards Balasubramanian G
  9. Hi, When I use the automation of register model by register assistant, in the video, it use the command 'vreguvm - gui' to translate the .csv file to register package. But When I input this command, it reminds me 'command not found'. what's the reason of that? The version I use is 10.2c_2. Do I need to install some package? If need, please tell me. I will ask the CAD administrator in my company to install it. And where can I get the csv templates mentioned in the mentor's video? Thanks
  10. I don't know if I'm posting in the right forum section, so I apologize in advance. I have a couple of questions about the UVM-ML architecture. For reference, I will be using the sc-sv unified hierarchy example, which is provided with UVM-ML-1.4.2. 1) In the sctop.cpp file, which looks like this: #include "uvm_ml.h" #include "ml_tlm2.h" #include "producer.h" #include "consumer.h" using namespace uvm; using namespace uvm_ml; // The environment component contains a producer and a consumer class env : public uvm_component { public: producer prod; consumer cons; env(sc_module_name nm) : uvm_component(nm) , prod("prod") , cons("cons") { cout << "SC env::env name= " << this->name() << endl; } void before_end_of_elaboration() { cout << "SC env::before_end_of_elaboration " << this->name() << endl; std::string full_initiator_b_socket_name = ML_TLM2_REGISTER_INITIATOR(prod, tlm_generic_payload, b_isocket , 32); cout << "SC env registered " << full_initiator_b_socket_name << endl; std::string full_initiator_nb_socket_name = ML_TLM2_REGISTER_INITIATOR(prod, tlm_generic_payload, nb_isocket , 32); cout << "SC env registered " << full_initiator_nb_socket_name << endl; std::string full_target_socket_name = ML_TLM2_REGISTER_TARGET(cons, tlm_generic_payload, tsocket , 32); cout << "SC env registered " << full_target_socket_name << endl; } ... UVM_COMPONENT_UTILS(env) }; UVM_COMPONENT_REGISTER(env) // Top level component instantiates env class sctop : public uvm_component { public: env sc_env; sctop(sc_module_name nm) : uvm_component(nm) , sc_env("sc_env") { cout << "SC sctop::sctop name= " << this->name() << " type= " << this->get_type_name() << endl; } ... UVM_COMPONENT_UTILS(sctop) }; UVM_COMPONENT_REGISTER(sctop) #ifdef NC_SYSTEMC NCSC_MODULE_EXPORT(sctop) #else int sc_main(int argc, char** argv) { return 0; } UVM_ML_MODULE_EXPORT(sctop) #endif What is the NC_SYSTEMC define and where is it used? What is UVM_ML_MODULE_EXPORT() and when is it used? 2) In file test.sv: import uvm_pkg::*; `include "uvm_macros.svh" import uvm_ml::*; `include "producer.sv" `include "consumer.sv" ... // Test instantiates the "env" and "testbench" which has a foreign child class test extends uvm_env; env sv_env; testbench tb; ... task run_phase(uvm_phase phase); `uvm_info(get_type_name(),$sformatf("SV test::%s %s", phase.get_name(), get_full_name()),UVM_LOW); while (1) begin #1 uvm_ml::synchronize(); end endtask ... `uvm_component_utils(test) endclass What is the uvm_ml::synchronize() function and when is appropriate to use it? If there are documents where I can find out more please mention them.
  11. Hi, While running simulation , i am getting the below mentioned error . Can anyone help me to fix this error. ncsim: *E,IMPDLL: Unable to load the implicit shared object. OSDLERROR: /prj/.../v/_sv_export.so: failed to map segment from shared object: Operation not permitted. ncsim: *W,LIBRUN: Could not load the dynamic library: ./INCA_libs/irun.lnx86.13.10.nc/librun System ERROR: ./INCA_libs/irun.lnx86.13.10.nc/librun.so: failed to map segment from shared object: Operation not permitted. ncsim: *F,NOFDPI: Function main not found in any of the shared object specified with -SV_LIB switchncsim: *E,IMPDLL: Unable to load the implicit shared object. Thanks Sidharth
  12. Mediatek is looking for verification engineers who are users of SV/UVM for their Bangalore center. Engineers in the experience range from 2-12 years can apply. If interested please send mail to ron.mediatek@gmail.com Essential Skills: Should have worked on at least one ASIC tapeout Hands on with SV/OVM/VMM/UVM Should have executed test planning at block/SoC level
  13. Hi there From the UVM users guide, a register read access can be executed as reg_model.BLK1.REG_FILE1.REG_1.read(status, rdata); But this mandates us to know the hierarchy of the register instantiation. ie., 'reg_model.BLK1.REG_FILE1' needs to be known to execute a read on register 'REG_1'. Is it possible to perform read/write access based on address instead of this hierarchy? Something like: generic_uvm_read (.address(0x0), rdata); In otherwords, we need not even know the register type or register instantiation hierarchy to issue a read access to that register. Can this be performed with UVM_REG? Requesting thoughts here. Best regards Balasubramanian G
  14. This is a online training batch taught by experts working in Semiconductor Industry. Course schedule is for 2.5 hours on Sat and Sun for 7 weeks. Graduates and working professionals can benefit from this training. For more details please email vlsitraining@sumerusolutions.com
  15. Hi there I couldn't find enough information about capturing whitebox information with respect to a register defined in IP-XACT standard. Could this be done somehow? The closest that could be found was WHITEBOX information with respect to models.(not registers) Though the register definition can be captured in IP-XACT XML, there isn't proper way to capture RTL implementation of a register in IP-XACT. Capturing RTL implementation of a register in IP-XACT XML would enable us to stitch UVM_REG backdoor access. (without vendorExtensions) We feel the urge/need to enhance IP-XACT standard regarding the same. Requesting thoughts regarding the same. Best regards Balasubramanian G
  16. Dear all, As we close in on delivering UVM 1.2 to the engineering community now is the time for you to read the docs, review the code, test the functionality. Or as they say forever hold your peace..... Once approved changing documentation requires another full review so really please do give your feedback ASAP. As a UVM user it is in your interest that UVM meets your requirements and your opinion is considered. There is a list of issues we know about within the Mantis database: http://www.eda.org/svdb/my_view_page.php If you want to view the code for a particular branch from sourceforge you can do so from your browser. http://sourceforge.net/p/uvm/code/ref/master/branches/ On the left click ""More Branches" UVM 1.2 will be built from the UVM_1_2 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2/tree/ At the time of writing the latest HTML docs are generated from RC4 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2_RELEASE_RC4_WITHHTMLDOC/tree/ It is just as easy to grab the latest code for you to run with your own projects for testing. A simple script can look like: #!/bin/csh -f mkdir $1; cd $1 ; git clone git://git.code.sf.net/p/uvm/code ; cd code ; git branch --track $1 origin/$1 ; git checkout $1 ; By passing in your branch name to the script it will checkout that particular branch for you. git_uvm.csh UVM_1_2 ; You can give feedback via your Accellera representation or local EDA person or provide feedback here. Time is of the essence so act today. thanks,
  17. Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog
  18. Version 5.0

    334 downloads

    This download contains a sample UVM environment that shows the use of IDesignSpec Free to generate a UVM Register Model. The input can be SystemRDL, IP-XACT, Word, Excel, XML etc. You can download the Free IDesignSpec Register Generator from here. You can use the included example as a ready reference to generate your own register model. You can use any or all of the IDesignSpec flavors: Word, Excel or Batch.
  19. hi, all, I'm a newer in learning UVM. With the support of many UVM experts, we can find many examples for learnning UVM. However, when I tried to have a taste on some examples using VCS to compile them, the Makefile is a headache for me. Could you please let me know how to write a good Makefile for compilation and running simulation in VCS? Thank you in advance! Liya
  20. I am learning UVM. So far I was able to create the following environment for my DUT. Agents with monitors, drivers and sequences for all of the input-output interfaces from my DUT. A top level UVM env. Sequences to send valid data to DUT. I yet to implement scoreboard. I'm having some trouble to understand how to handle scenarios like following: For one of my tb->dut interfaces, TB needs to wait for an event (or transaction) from DUT. Once it receives the transaction from DUT, TB needs to send back a response. What is the best way to implement this? How can I monitor DUT transaction from sequence? I assume I need to wait for an event or something similar which will tell me that DUT has a new valid output in its interface. My agents have monitors which will monitor any new output signals from DUT. So, do I need to somehow bring this data from agent's monitor to my test/sequence class? I know that monitor has an analysis port and it can be used to send received data to scoreboard for checking. So, do I need to use the same port to read DUT output data, create valid response and send it to DUT? Thanks!
  21. Event: Experiences of Using UVM - DVClub Shanghai Date: 28 March 2014 Time: 14.40 to 17.30 (CST) 07.00 to 09.30 (GMT) Organizer: Mike Bartley @TVS Roman Wang @AMD Charles Sun @Topbrian Sponsors: ARM, Cadence, Mentor and Synopsys The next DVClub Shanghai webcast event takes place on Friday, 28th March and will focus on the experience of UVM! Why not register to hear five speakers bringing their own unique perspective: Agenda (CST) 14.40 Arrival and Networking 15.00 Mike Bartley, Test and Verification Solutions - Verification Challange Outlook in 2014 15.30 Uwe Simm, Cadence - UVM1.2: What's Now and What's Next? 16.00 Yuanpeng Su, Synopsys - UVM Best Practices and Debug 16.30 Albert Chiang, Mentor Graphics - UVM, The Next Phase 17.00 Roman Wang, AMD - Are you Suffering to Handle on-the fly Events in Complex UVM Scenarios? 17.30 Close Registration and additional details of the presentations and speakers can be found here https://www.eventbrite.co.uk/e/dvclub-shanghai-28-march-2014-tickets-10200850017 Register the remote way if you could not access locally. DVClub Shanghai is organized by TVS & Topbrain who are committed to making DVClub Shanghai accessible to everyone and you can join the meeting remotely via the Internet or physically in shanghai. If you attend remotely why not do what many other companies do - book a room and invite your colleagues along so you can discuss and debate the topic.
  22. UVM doesn't have to be serious all the time, does it? fyi... we got a new dog to keep us company in the office. His name is uvm. He's a good dog. He does tricks, but he can't jump. www.realityreused.com/support.html -neil
  23. Hi all, What exactly is the difference between uvm_hdl_force and uvm_hdl_deposit? The UVM Class reference document doesn't provide much explanation. Please help. Thanks, Shreyas
  24. Can anyone here recommend me chapters needed to read in questasim user guide so as to simulate uvm systemverilog environment ,, let's have assumption that I have no knowledge about simulator commands interface ,,, thanks in advance
  25. What is the difference between configuration object and configuration space in UVM?
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