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  1. The cook book from Mentor tells following and in another thread, the moderator also suggested against using the sub phases of run. However in one of my projects, I do find the need for using them (and infact we had an internal implemention of something similar in our previous OVM version). Are there any thing happening on this front? Is there a risk in using the sub phases if some of that changes in a future version? "The Accellera UVM committee is still developing the use models and APIs for new UVM phasing as it relates to sequences and transactors. In the mean time, our recommendation is to wait until that work is done and the API is stable. There are a number of future articles in this section which will be available here at that time, and which will describe our recommendations for using this technology. These include: How to make your testbench phase aware [Not yet available] How to manage sequences in the context of phasing [Not yet available] How to design reusable transactors that work in the context of phasing [Not yet available] "
  2. Let's say I have the following DUT. The UVM environment contains a chain of models/predictors. Input data flows down this chain and generates the expected CHIP output, which is compared to actual. Pros: verifies top-level functionality. Cons: Does not verify block level functionality. A good start, but I'd like to also verify the blocks in a system setting. So, I create block-level environments, then reuse them at the top level. Awesome, but wait a minute. I still need the top-level verification (Input-to-Output) like in the first example. However, all 3 of my block predictors are being used in their corresponding environments' scoreboards, hooked up to the RTL, via agents. How does one do both? Surely I'm not supposed to instantiate duplicate copies of my block level predictors to create the end-to-end model chain...
  3. Hi, We are using snps ralgen to generate the regmodel. It appears that the ralgen creates only the default map. We would like to have 2 maps for 2 separated if masters. Is there an online example for such case? A post gen script can do one of the following 2 options: 1. add another instance of uvm_reg_map and copy/clone the ready map after finished build 2. add another instance of uvm_reg_map, and duplicate any map1.add_reg and map1.add_submap to map2 Which is preferable? Thanks! Elihai
  4. I see uvm_sequencer_base::wait_for_grant (UVM 1.1d) is a virtual task but accesses a local int g_request_id - is this not a bad coding style? If I were to override this virtual method for debug with much of the code intact tool throws an error for his local bar in a derived SQR class. I extended a SQR class and copied all the code for wait_for_grant and started tweaking - couldn't proceed with that debug due to this member being local. Should it be protected instead of local? Thanks Srini wwww.go2uvm.org
  5. I need to have two uvm_tlm_target_socket in a class and I need to do different set of things with the data received via two sockets. I was thinking if it is possible to have two implementation of b_transport task. I am aware of how we can have multiple analysis port imp and use uvm_analysis_imp_decl(_something) and we can have a "write_something" implementation. Is something similar available for uvm_tlm_target_socket? Regards, Gautam
  6. Is it possible to do a uvm_config_db::set() for an object of derived class type using the base class handle and later do a uvm_config_db::get() of same object using the derived class handle Since a base class handle can be used to point to a derived class object and later typecase, I thought this would work, but doesn't seem to be so. Any help will be appreciated? Here is an example class BaseA ; endclass class DerivedA extends BaseA endclass 1) Set config_db DerivedA a1; a1 = DerivedA::create() uvm_config_db#(DerivedA)::set(this, "" , "myobj", a1); 2) Get config_db BaseA a1; DerivedA a2; uvm_config_db#(BaseA)::get(this, "" , "myobj", a1); $cast(a2, a1);
  7. I'm trying to run uvm-systemc on macosx. Link to download: http://accellera.org/images/downloads/drafts-review/uvm-systemc-1.0-alpha1.tar.gz In the install flow, ../configure works fine, but on make i get this error: Making all in macros CCLD libmacros.laar: no archive members specifiedusage: ar -d [-TLsv] archive file ... ar -m [-TLsv] archive file ... ar -m [-abiTLsv] position archive file ... ar -p [-TLsv] archive [file ...] ar -q [-cTLsv] archive file ... ar -r [-cuTLsv] archive file ... ar -r [-abciuTLsv] position archive file ... ar -t [-TLsv] archive [file ...] ar -x [-ouTLsv] archive [file ...]make[4]: *** [libmacros.la] Error 1make[3]: *** [all-recursive] Error 1make[2]: *** [all-recursive] Error 1make[1]: *** [all] Error 2make: *** [all-recursive] Error 1 I've looked online, and it seems that it is a makefile problem. However the uvm-systemc makefile is way to complex for me to comprehend where the issue could reside. Any ideas on why is this happening? Thanks
  8. Hi, I notice something interesting in the build_phase order of uvm_component. The uvm_component at the same level are build in the alphabetatical order of the instance name. I expect the build order would be the same as the order I call the factory create function. I am wondering is the alphabetatical build order an intended feature of UVM or just some artifact of the implementation? I couldn't find any reference to this behavior in the UVM user guide or the class reference library. Thanks. Horace
  9. In case of UVM ,config_db can be accessed in any component or object which helps mainly the dynamic creation of component/models.Whether any option is present in SYSTEM C ?
  10. Hi all, I'm new with UVM and I came across a problem. I am working on an AXI RD VIP using UVM and I have the following issue. In the data_phase (the data channel driving) from the MASTER driver, I need to drive the RREADY signal. There are 3 handshake types described in the protocol specifications: valid before ready, ready before valid and ready and valid at the same time. In case of valid before ready, I want to wait a certain number of clock cycles ( delay ) from the time that RVALID asserted and then to assert the RREADY signal. From my understanding, all the delay information should come from the transaction(sequence_item). The problem is that I generate a new transaction (sequence_item) with get_next_item only when I drive the address channel (in address_phase); The data_phase works in parallel with the addr_phase and its independent of the address phase. Also the data_phase needs multiple delay values (one for each data received from DUT, ex. arlen+1) while I only generate one transaction that contains the address channel informations. Code example: task run_phase(uvm_phase phase) fork forever begin ... seq_item_port.get_next_item(req); address_phase(req); seq_item_port.item_done(); end forever begin data_phase(); end endtask : run_phase task address_phase(axi_item item); // Drive the address channel ... endtask : address_phase task data_phase(); // Wait for the rvalid signal while(!vif.rvalid) @(posedge vif.clk); // Insert delay between rvalid assertion and rready assertion repeat(<problem!!!!>) @(posedge vif.clk); rready = 1; ... endtask : data_phase I don't know what variable (sequence_item variable) to set in the <problem!!!> Can anyone give me an advice regarding this problem. I repeat, I want all timing related data to be set from the sequence_item Regards, Adrian
  11. Hello, I'm trying to implement an AXI Slave VIP and have few questions regarding the implementation. In this case, the DUT is the master. The AXI Slave checks the interface for valid read /write signals and performs a read/write operation from a memory model. It returns back the write response/read data back to the DUT. 1. Since this is a slave VIP , do I need a slave sequence which runs forever sending transactions to the driver ? This is similar to the UVM example where the monitor and sequencer are connected by an analysis port and the sequence calls the peek function to check if a valid transaction is available from the monitor. (OR) 2. Can I skip the sequence/sequencer part and just connect my monitor and driver using an analysis port and pass on the observed transaction from the monitor to the driver for further action ? (OR) 3. Im thinking of a 3rd alternative of just using the monitor to the observe the interface and drive back the write response/ read data back using the monitor itself and leave the driver empty. Please let me know your valuable thoughts and suggestions. Thanks, Madhu
  12. Hi, As per my understanding, connect_phase does not start until all build_phase do not complete. How is this mechanism controlled? I did not find anything in uvm reference manual about this. Please let me know if there is any. Thanks.
  13. Hi, I have a doubt about requirement of raise/drop_objection. Why does a compiler need objections in run_phase? Why can it not just wait for time given like 100ns as following example? Ex. task run_phase(uvm_phase phase); //phase.raise_objection(this); #100ns; //phase.drop_objection(this); endtask
  14. Version 2016-06-24

    415 downloads

    This document is a printable version of the Easier UVM Coding Guidelines from Doulos. You are free to use these guidelines directly, to merge them into your own company-specific UVM coding guidelines, or merely to borrow some of the ideas. These coding guidelines are offered by Doulos for the benefit of the UVM community. They are not officially endorsed by Accellera.
  15. Hi all, I'm doing verification for an PHY between SPI master and a memory chip. I make two agents one for master to transfer the request, one mimics the memory slave to reply. PHY will be hooked up to two interfaces that of SPI Master and Memory. During sending request and reply data, Chip Select Pin (in SPI interface) must go low to enable the transaction. But I don't know how to control this pin when It sends the reply from memory. Because this pin is not an interface of memory slave agent. Could anyone give me some advice? Could I use phases to control the env that has different agents? Thank you, Nhat
  16. To view this announcement on the IEEE web site click here. Purpose Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. Need for the Project As the electronics industry builds more complex systems involving large numbers of components, the challenge of verifying such systems multiplies by orders of magnitude. In order to bring costs and time to market down, standardization must happen to enable as much modularity and reuse across verification components as possible. The UVM standard will propagate an API that will manage this explosion in verification complexity, allowing the entire industry to write and reuse verification components both (a) internally in companies having geographically widespread teams, and (externally between vendors and user companies in the electronics industry, who are developing, selling and using verification components Call for Contribution Please review the IEEE P1800.2 ™ PAR and, if you are interested in participating, Register for the first working group meeting scheduled to occur on August 6th, 2015 from 12pm – 2pm Eastern Daylight Time (EDT) / 9am – 11am Pacific Daylight Time (PDT). Please feel free to connect with the Working Group Chair, Thomas Alsop at thomas.r.alsop@intel.com or IEEE-SA staff Jonathan Goldberg at goldberg.j@ieee.org directly for further information.
  17. Hi, I am using uvm_resource_db to set and get any component configuration. But I am getting an error saying configuration object is not found. Its something that its not able to get the config object from configuration space. In env build_phase, I do set the configuration as below: uvm_resource_db#(io_config)::set("io_agent_0*","io_agent_config",m_io_config,this); And in io_agent, below code is used to get the configuration: assert(uvm_resource_db#(io_config)::read_by_name(get_full_name(),"io_agent_config",cfg,this) else uvm_report_fatal("io_agent","not able to get the configuration object"); Kindly let me know if there is anything wrong in the above usage. And also, can I do setting configuration through uvm_resource_db and getting it through uvm_config_db. Thanks A.Sunitha
  18. a usual way to do it is to create a wrapper object and push the wrapper into config_db. Then get this wrapper object from config_db and assign it to the virtual interface pointer (not mentioning the details here) Creating the virtual interface container wrapper parameterized to the strongly typed interface helps here. but in the uvm component, a pointer needs to be created for the parameterised interface. If not wanting the classes to be parameterized, how the virtual interface handle can be created without specifying the parameter as either a default parameter in base class or override is necessary for creating handle?. The component will get the wrapper object from config_db and assign it (the virtual interface in the object) to the virtual interface pointer Thanks.
  19. This is a online training batch taught by experts working in Semiconductor Industry. Course starts with System Verilog and covers advanced level UVM. Course schedule is for 2.5 hours on Sat and Sun for 7 weeks. Graduates and working professionals can benefit from this training. Next batch starting on July 11th, 2015! For more details please email vlsitraining@artoflivinghet.org Course schedule is for 2.5 hours on Sat and Sun for 7 weeks. Graduates and working professionals can benefit from this training. For more details please email vlsitraining@artoflivinghet.org
  20. Hi all, First I apologize if I am using the wrong forum for the question. Please, I would like to know whether someone here could give updates on uvm-sc status. When will a first public release be available ? Regards
  21. Hello there, As per Mentor's UVM guidelines 5.2 [1], reset_phase() will be obsolete in future releases. During DVCon 2014, Cadence recommends to use run_phases() on slide 5 of [2]. With the release of UVM-1.2, I believed that the sub-phases of run_phase are now stable and clean. Now with the recommendations above, it seems that the it's better to stick with run_phase() itself. As UVM delelopers, what are your views about it ? What do you recommend ? My intention is not to start a flame war of any kind. But to understand which route to opt in order that most of my UVM code would be compatible with UVM 1.3. All in all, it appears that there is a miscommunication on the web. [1]: https://verificationacademy.com/cookbook/UVM/Guidelines [2]: http://proceedings.dvcon-europe.org/2014/presentations_and_papers/T5_3_presentation.pdf regards, Chitlesh
  22. Hi All, I am facing an issue: One of the register field is configured as : field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1); field_a.set_compare(UVM_NO_CHECK); While doing a reset test, first I reset model then start test. But test fails with : UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00) Basically the fields declared as RO and UVM_NO_CHECK goes X ? Any idea what I am missing or doing wrong ? Thanks.
  23. I am trying to run a couple of test cases using script.But I am getting an error message after running the first test case.This stops the simulation.I am attaching the LOG with this mail.I don't understand why this is happening. I checked previous posts and added +UVM_OBJECTION_TRACE in the vsim command.But I am not able to find out the cause of the error.Can anybody help me?? # UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top raised 1 objection(s): count=1 total=1 # UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object uvm_test_top): count=0 total=1 # AT TIME=0,APB MASTER IN RESET MODE # AT TIME=1200000,APB MASTER IN ACTIVE MODE # AT TIME=45400000,*************************** EXPECTED_DATA=1792474624,RECEIVED DATA=1792474624 # AT TIME=186600000,*************************** EXPECTED_DATA=222,RECEIVED DATA=222 # AT TIME=231800000,*************************** EXPECTED_DATA=1504340502,RECEIVED DATA=1504340502 # AT TIME=349000000,*************************** EXPECTED_DATA=2367782205,RECEIVED DATA=2367782205 # UVM_INFO Test_Cases/my_test.sv(40) @ 349000000: uvm_test_top [root objections] # The total objection count is 1 # --------------------------------------------------------- # Source Total # Count Count Object # --------------------------------------------------------- # 0 1 uvm_top # 1 1 uvm_test_top # --------------------------------------------------------- # # UVM_INFO Test_Cases/my_test.sv(43) @ 349000000: uvm_test_top [my_component objections] # The total objection count is 1 # --------------------------------------------------------- # Source Total # Count Count Object # --------------------------------------------------------- # 1 1 uvm_test_top # --------------------------------------------------------- # # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_test_top dropped 1 objection(s): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_test_top all_dropped 1 objection(s): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source object uvm_test_top): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source object uvm_test_top): count=0 total=0 # UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 349000000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase # # --- UVM Report Summary --- # # ** Report counts by severity # UVM_INFO : 12 # UVM_WARNING : 0 # UVM_ERROR : 0 # UVM_FATAL : 0 # ** Report counts by id # [OBJTN_TRC] 6 # [Questa UVM] 2 # [RNTST] 1 # [TEST_DONE] 1 # [my_component objections] 1 # [root objections] 1 # ** Note: $finish : C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430) # Time: 349 us Iteration: 68 Instance: /my_top # 1 # Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430 # Simulation Breakpoint: 1 # Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430 # MACRO ./run_do PAUSED at line 18
  24. Hi, I am diagnosed with ‘Wrist tendinitis’/’tenosynovitis’ due to RSI (Repetitive Strain Injury). Hence I started using speech recognition as much as possible. On windows, controls are 80% accurate and dictation is 50% accurate. With practice, I am trying to use keyboard and voice recognition just the same way a pianist would sing. I think with the wealth of research in speech recognition, it is possible to get a decent accuracy 1. for coding (UVM, systemverilog) as there are predefined set of keywords, classes, functions etc. 2. for GUI tool controls An example of coding: to see in editor "class myenv extends uvm_env;" I would Say: "class" type: myenv Say:"extends uvm_env;" For GUI usage, tool vendors/users could come up with a number of useful features similar to keyboard shortcuts. These features may be implemented both on Windows and Linux platforms. (Hope in few years engineers are able to dictate their code into a tool and debug it too! Also wish there is research on use of various HCIs for EDA) Thanks for reading my request! Regards, Kal Gandikota P.S.: I used windows speech recognition to write this e-mail as I am suffering from wrist pain. Please kindly ignore grammar mistakes.
  25. Hello all, How would one go about leveraging UVM for ES level DUT verification? Most of the stuff from RTL still applies but how do we correctly use the driver and monitor if the DUT does not have signals, but has TLM ports/sockets. The UVM states that one agent should be used per interface, but the problem on the ESL is that there are no signals so how do we monitor TLM ports/sockets with the monitor, while the driver stimulates the DUT? How do we connect ports/exports to the driver, monitor and the DUT simultaneously? A solution without using analysis ports would be great. I've included an image for easier reference. I guess that on ES level the monitor and driver are redundant, but then the sequencer would have to send packets to a checker and the DUT simultaneously, which would require either two ports or an analysis port. Another option would be to keep everything the same as in the image and have two ports, one from the driver to the DUT, and one from the driver to the monitor and send packets simultaneously. Please state your thoughts on this.
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