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  1. Hi I'm learning SystemC language and I made a JK flipflop and 8bit counter using 8-JK flipflop there's no problem building project but if I running GTKwave using vcd trace file it cannot show anything. please help me //test.h #include "systemc.h" SC_MODULE(test) { sc_in<bool> clock; sc_out<bool> go; void do_test(); SC_CTOR(test) { SC_CTHREAD(do_test, clock); go.initialize(0); } }; //test.cpp #include "test.h" void test::do_test() { go.write(1); while(true) { wait(1); } } //JK_FlipFlop.h #include "systemc.h" SC_MODULE(JK_FlipFlop) { sc_in<bool> Input_J; sc_in<bool> Input_K; sc_in<bool> Input_clk; sc_out<bool> Output_q1; sc_out<bool> Output_q2; void do_jk(); SC_CTOR(JK_FlipFlop) { SC_METHOD(do_jk); sensitive<< Input_clk.neg() << Input_J << Input_K; Output_q1.initialize(0); Output_q2.initialize(1); } }; //JK_FlipFlop.cpp #include "JK_FlipFlop.h" void JK_FlipFlop::do_jk() { if(Input_J == true && Input_K == false) { Output_q1.write(1); Output_q2.write(0); } else if(Input_J == false && Input_K == true) { Output_q1.write(0); Output_q2.write(1); } else if(Input_J == true && Input_K == true) { Output_q1.write(!Output_q1); Output_q2.write(!Output_q2); } else { Output_q1.write(Output_q1); Output_q2.write(Output_q2); } } //counter.h #include "JK_FlipFlop.h" SC_MODULE(counter) { sc_in<bool> clk, go; sc_out<unsigned char> value; sc_signal<bool> connect1; sc_signal<bool> connect2; sc_signal<bool> connect3; sc_signal<bool> connect4; sc_signal<bool> connect5; sc_signal<bool> connect6; sc_signal<bool> connect7; sc_signal<bool> connect8; sc_signal<bool> no1, no2, no3, no4, no5, no6, no7, no8; JK_FlipFlop *FF1; JK_FlipFlop *FF2; JK_FlipFlop *FF3; JK_FlipFlop *FF4; JK_FlipFlop *FF5; JK_FlipFlop *FF6; JK_FlipFlop *FF7; JK_FlipFlop *FF8; void do_count(); SC_CTOR(counter) { FF1 = new JK_FlipFlop("jk1"); FF2 = new JK_FlipFlop("jk2"); FF3 = new JK_FlipFlop("jk3"); FF4 = new JK_FlipFlop("jk4"); FF5 = new JK_FlipFlop("jk5"); FF6 = new JK_FlipFlop("jk6"); FF7 = new JK_FlipFlop("jk7"); FF8 = new JK_FlipFlop("jk8"); FF1->Input_clk(clk); FF1->Input_J(go); FF1->Input_K(go); FF1->Output_q1(connect1); FF1->Output_q2(no1); FF2->Input_clk(connect1); FF2->Input_J(go); FF2->Input_K(go); FF2->Output_q1(connect2); FF2->Output_q2(no2); FF3->Input_clk(connect2); FF3->Input_J(go); FF3->Input_K(go); FF3->Output_q1(connect3); FF3->Output_q2(no3); FF4->Input_clk(connect3); FF4->Input_J(go); FF4->Input_K(go); FF4->Output_q1(connect4); FF4->Output_q2(no4); FF5->Input_clk(connect4); FF5->Input_J(go); FF5->Input_K(go); FF5->Output_q1(connect5); FF5->Output_q2(no5); FF6->Input_clk(connect5); FF6->Input_J(go); FF6->Input_K(go); FF6->Output_q1(connect6); FF6->Output_q2(no6); FF7->Input_clk(connect6); FF7->Input_J(go); FF7->Input_K(go); FF7->Output_q1(connect7); FF7->Output_q2(no7); FF8->Input_clk(connect7); FF8->Input_J(go); FF8->Input_K(go); FF8->Output_q1(connect8); FF8->Output_q2(no8); SC_METHOD(do_count); sensitive << clk; sensitive << go; } }; //counter.cpp #include "counter.h" void counter::do_count() { unsigned char local_value = 0; local_value |= (FF1->Output_q1)<<0; local_value |= (FF2->Output_q1)<<1; local_value |= (FF3->Output_q1)<<2; local_value |= (FF4->Output_q1)<<3; local_value |= (FF5->Output_q1)<<4; local_value |= (FF6->Output_q1)<<5; local_value |= (FF7->Output_q1)<<6; local_value |= (FF8->Output_q1)<<7; value.write(local_value); } //main.cpp #include "counter.h" #include "test.h" int sc_main(int argc, char* argv[]) { sc_signal<unsigned char> Value; sc_signal<bool> Go; sc_clock CLK("clock", 50, SC_NS); counter COUNTER("ccc"); COUNTER.clk(CLK); COUNTER.go(Go); COUNTER.value(Value); test TST("TST"); TST.clock(CLK); TST.go(Go); sc_trace_file *tf = sc_create_vcd_trace_file("wave"); sc_trace(tf, COUNTER.connect1, "jk1"); sc_trace(tf, COUNTER.connect2, "jk2"); sc_trace(tf, COUNTER.connect3, "jk3"); sc_trace(tf, COUNTER.connect4, "jk4"); sc_trace(tf, COUNTER.connect5, "jk5"); sc_trace(tf, COUNTER.connect6, "jk6"); sc_trace(tf, COUNTER.connect7, "jk7"); sc_trace(tf, COUNTER.connect8, "jk8"); sc_trace(tf, CLK, "clock"); sc_trace(tf, Value, "SystemC value"); sc_start(20000, SC_NS); sc_close_vcd_trace_file(tf); return(0); } test is making signal always true jk flip-flop working only falling edge so I'm using clk.neg() counter have 8 flip-flop. first flip-flop clock accept main clock and second flip flop accept first flip-flop's q1 value the other flip-flop connected same way to second flip-flop is there any problem?? I can't find any problem but I can't see anything in GTKwave please tell me why. I need your help (P.S : Actually I can't speaking English very well. so please understand I'm using wrong grammar or vocabulary. Thanks)
  2. Hi all, I am working with sc_fixed point types in systemc and i tried a small code with the usage of fixedpoint types. #define SC_INCLUDE_FX #include "systemc.h" #include <stdlib.h> //for srand() and rand() SC_MODULE(rand){ sc_out<sc_ufixed<8,8,SC_TRN,SC_SAT> > output; sc_ufixed<8,8,SC_TRN,SC_SAT> A; void process(){ while(true) { wait(19, SC_NS); A=rand() % 254 ; // range 0 to 253 output.write(A); } } SC_CTOR(rand) { SC_THREAD(process); } }; The above code is just a source module which provides the rand numbers in the fixed point format to the next module. But when i compile i am getting the syntax error as "sc_ufixed symbols could not be resolved" Even i defined locally the SC_INCLUDE_FX macro to work with the fixed point types. But i cant figure out what is the syntax problems while working with fixed point types. when i work the same with the integers, it works fine. Note: i am working in ubuntu 12.04 OS in eclipse C++ software. please help me to proceed with a solution
  3. Hi all, i am trying to translate a simulink model to system c module. The simulink block is a source block where it generates random number in the range of [ 0 , 253 ] and with a explicit sample period( the block produces outputs and if appropriate, updates its internal state) of 9 ns, and the output of this block is given to the next block with a latency of 1 sample period. i tried to translate this block to a system c module as shown below: #include "systemc.h" #include <stdlib.h> //for srand(uint) and rand() SC_MODULE(RNG){ sc_in_clk clk; sc_out< sc_uint > output; sc_uint A; void process(){ // while(true) { wait(9, SC_NS); // Timed sampling, based on simulink block sample time A=rand() % 254 ; // do the process wait(9, SC_NS); // delaying the output for 1 latency ie. 1 sample period output.write(A); // then write the output } } SC_CTOR(RNG) { SC_THREAD(process); sensitive<< clk.pos(); } will the above code imitates the simulink model with its specifications as i prescribed? please have a look and let me know how i can proceed for the solution. Thank you.
  4. Hell All, I posted a question entitled "Determining source of events using global fifo" on Sep 9, 2013. Surprisingly, I have not got a reply for this post so far. What is wrong with this post? Any idea? Can anyone see my post? Thanks, Alireza
  5. After Signal/Port binding, when signal changed, the sensitive list will cause SC_METHOD registered method to run. When I'm implementing the SystemC version, I met this warning W571. To be honest, I think this warning is correct because there is no activity. But Why there is no activity where I thought there should be is the question. The problem happens when call sc_start() the second time; I suspect that the binding between signal/port is not handing well. SC_MODULE ( MyClass ) { SC_CTOR(MyClass) { SC_METHOD(eventListener); dont_initialize(); sensitive << m_event; } void eventListener() { Event* event = m_event.read(); ... delete event; } } int sc_main (int argc, char* argv[]) { sc_signal<Event*> eventSubject; MyClass context("CONTEXT"); context.m_event(eventSubject); //bind signal to port, m_event is the port while(true) { getline(cin, in); ... eventSubject = new Event(); sc_start(); } }
  6. Hello, How can i plz define an sc_lv with a variable width ? Thank you for your help
  7. I have designed and developed RTC using systemc language. But there is mismatch between this RTC and original timing? Can anyone tell me the reason for this?
  8. Hello all, What is the difference between mutex and seamaphore? Regards Amit
  9. Hi, I need to make a timing checks for the input signals of a module (e.g., check set-up and hold times are not violated, check Pulse width). Is there any method which would let me do this. If further information is needed, please contact me! Thank you in advance for your help.
  10. Hi, everybody. I'm needing use netbeans IDE to develop systemC projects on windows 7. I installed the netbeans 7.3 and the cygwin with gcc 4.8. the systemC already be installed and working normally in cygwin (I already have used...). recently, I installed systemC on netbeans, that use cygwin compiler, and I can use normally too: netbeans "recognize the systemC language", compile and execute my projects. my only problem is that, on netbeans, the "sc_signal<bool>" is don't recognize. =S the "sc_signal<int>" work, "sc_signal<sc_logic>" work and all the others.... the code with "sc_signal<bool>" compile normally on the netbeans, but the signal of this type is always underlined in red, indicating an error. the problem is on netbeans, because the code compile without any error (with gcc of the cygwin)... on netbeans appear "Unable to resolve the identifier 'write'" (for example). can anyone help me? (if nobody understand, I can detail) sorry my english errors and thanks a lot.
  11. India SystemC User Group Conference (ISCUG) A platform to discuss the SystemC based next generation methodologies for design and verification of Electronics Systems (Semiconductor Chips + Embedded Software) Tutorial Day: April 14, 2013 (Sunday) Conference Day: April 15, 2013 (Monday) Venue: Noida, India Register for the event at www.iscug.in. Early bird discount ends on February 28th, 2013. To receive regular updates about the event, register your email at www.iscug.in and follow www.facebook.com/iscug. For sponsorship opportunities, contact info@iscug.in About ISCUG The India SystemC User's Group (ISCUG) organization aims to accelerate the adoption of SystemC as the open source standard for ESL design. ISCUG provide a platform to share the knowledge, experiences and best practices about SystemC usage. ISCUG organize an annual conference which provides a platform for the SystemC beginners, the SystemC experts, ESL managers and the ESL vendors to share their knowledge, experiences & best practices about SystemC usage. The event will also be useful for: SoC Architects involved in architectural exploration, performance optimization, power optimization etc.. Embedded software engineers who want to explore usage of Virtual Platforms for embedded software development Chip verification engineers who want to explore SystemC based verification methodologies Chip design engineers who want to explore SystemC as the language for chip design at higher abstraction level The event is designed on the pattern of similar events happening worldwide: NASCUG, ESCUG, Japan SystemC Forum, etc. Participate You may participate in ISCUG as a speaker. Submit your abstract at www.iscug.in before February 15, 2013. The abstract will be reviewed by the technical review committee; the committee reserves the right to make final decision on speaker selection. You may present a topic related to SystemC modelling, covering virtual platforms, transaction-level modeling, high-level synthesis, SystemC-AMS, modeling for performance analysis, modellng for architectural exploration, SystemC-based SoC verification methodology, or any other topic related to SystemC modeling. You may also present a success story of SystemC adoption in your company. Tutorial Day: There will be a full day of tutorials running in parallel. To participate as a speaker, send details to info@iscug.in. First Half (Before Noon): SystemC and TLM 2.0 Introductory Tutorial Second Half (After Noon): Two/three tracks in parallel (details yet to be finalized) Advanced modeling techniques Virtual platforms for embedded software development and pre-silicon HW/SW co-verification High-level synthesis using SystemC SystemC-based verification methodologies Contact Web: www.iscug.in Email: info@iscug.in
  12. Hi everybody, Do I need to do any modifications on my SystemC code in order to simulate it on ModelSim 6.5 Se? And, is there a simple tutorial for this? (The ModelSim User's Manual didn't really help me) Otherwise, is there a better (/easier) simulator? compiler/simulator? Thanks
  13. Hi, I am new to systemc. I am writing systemc simulator for windows. I need the user to configure and read registers and view statistics. i want it to do it using GUI (online) and not using files. is there any written example for that? Are there any recommended tools? tx, Smadar.
  14. Following are European SystemC Users' Group events at the DATE Conference 2013 in Grenoble, France. 27th European SystemC Users' Group Meeting Tuesday March 19th, 2013 6:30pm - 9:30pm Room TBA Join the Accellera update and town hall meeting around Accellera technologies and standards. We give insights into their influence and requirements for future design strategies. More information, including registration and the final program, will be available at: http://www.ti.uni-tu...10.0.html?&L=0/. European SystemC Users' Group Workshop ESL -- Putting the Pieces Together: Integrating SystemC Design and Verification with AMS and Algorithm Design Friday March 22nd, 2013 8:30am - 4:50pm Room TBA This full-day workshop is focused on the integration of SystemC design and verification with AMS and algorithm design. It gives deep insights on how techniques may collaborate and converge. These topics are gaining more and more interest because a seamless integration of all relevant design and verification techniques is crucial. Besides digital hardware design, this is substantially important for the areas of algorithm and AMS design. The keynote from STMicroelectronics discusses the challenges of design flow integration in multi physical domain applications. The workshop includes four invited sessions from TU Kaiserslautern, NXP, Fraunhofer IIS, and Bosch -- providing knowledge about the core technologies, their application, and integration into ESL design flows. The core session’s part is complemented by an interactive discussion with the audience. This session is organized in town hall meeting style. This event requires registration. For an agenda and to register, see http://www.date-conf...nce/workshop-w1.
  15. Hi, I am trying to write a SystemC/TLM front-end. To do so, I need SystemC grammar (at least the TLM part). Does anybody know how and where I can find it? Thank you, Reza
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