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Hello, I've scoured the internet and this forum for what I imagine will have a very simple solution. Apparently I am not describing it sufficiently. I have a SystemC model comprised of a handful of registers, and single memory bank. I would like to implement TWO blocking transport interfaces to this model. If I implement a single blocking transport ( via inheritance of b_transport ), the method has access to all the model resources. If I want two b_transport interfaces, I've had to move them to channels, which are then instantiated in the model. These channels do not have ac
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Hi, experts, I met such a problem. Here are the codes and the vcs reports: -------codes-------- class my_env extends uvm_env; my_sub_env subenv[]; ... // build phase function void build_phase(uvm_phase phase); ... subenv=new[10]; for (int i =0; i <10; i++) begin subenv = my_sub_env::type_id::create(sformatf("subenv%0d", i), this); end ... endfunction: build_phase // connect phase function void connect_phase(uvm_phase phase); ... foreach(subenv) begin reg_R.a_map.set_sequencer(subenv.v_
