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  1. Hi, I have a top level reg map set up as below. In my adapter I am trying to retrieve all the registers by address of incoming reg_item in bus2reg function to simulate burst condition. The get_reg_by_offset call returns null every time. I don't understand why the address is not found considering all the registers have unique offsets. Infact I retrieved the base address of the incoming reg_item to check if I can the register before incrementing for next offset, but it cannot find the register with base address. Any help is appreciated. Top register file: TOP_map = create_map(.name("TOP_map"), .base_addr('hFE00), .n_bytes(1),.endian(UVM_LITTLE_ENDIAN),.byte_addressing(1) ); default_map = CONTROL_TOP_map; TOP_map.add_submap(this.int_reg_blk.I2C_INT_map, .offset(8'h7C)); TOP_map.add_submap(this.scan_blk.SCAN_CTL_map, .offset(8'h84)); TOP_map.add_submap(this.ctrl_int_reg_blk.HOR_CTRL_map, .offset(8'h94)); TOP_map.I2C_INT_map.add_hdl_path("********", "RTL"); //didn't want to add proprietary code paths get_reg_by_offset call uvm_reg_item in_item = get_item(); base_addr = in_item.map.get_base_addr(); if(!(in_item.map.get_reg_by_offset(base_addr))) `uvm_error(get_type_name(), "Register not found in reg map") else registers[i] = in_item.map.get_reg_by_offset(base_addr+1);
  2. Hi all, I got a question regarding RAL. Assuming there are 2 registers A and B whose width are 8 bits and 16 bits respectively and the bus width is 8 as well. The two UVM registers are created by new(name, 8, UVM_NO_COVERAGE) and new(name, 16, UVM_NO_COVERAGE) for defining their own width. Register A and B locate at address 0 and 1-2 as the address is byte aligned. An user defined register map is created uvm_reg_map my_map = create_map("my_map", 0, 1, UVM_LITTLE_ENDIAN, 1); my_map.add_reg(reg_A, 0, "RW"); my_map.add_reg(reg_B, 1, "RW"); After reg_B.write(status, 16'habcd, .path(UVM_FRONTDOOR)), I would expect 2 transactions with 8 bits each appearing on the bus. However, there is only one access of h'cd to address 1. The other one never comes and it ends up throwing an error "There are 1 incomplete register transactions still pending completion" which is caused by a check on outstanding register accesses pending in predictor in check phase. I tried to find out how the original data value in uvm_reg_item gets split in reg2bus() function. It seems correct that the original data in uvm_reg_item is h'abcd and split to h'cd in uvm_reg_bus_op. But again the other part of data does not come. Also tried to search for answer from other places, for instance the same issue here https://verificationacademy.com/forums/uvm/how-handle-registers-are-wider-bus, it didn't help much unfortunately. If you have any clue about this, please leave your comments. Thanks.
  3. We are glad to open our popular, free #UVM JDI eBook for instant download now starting from 1-Jan-2021 via: https://tinyurl.com/uvmpdf Thanks to Ajeetha Kumari , Ben Cohen Shankar Hemmady and many more who inspired us to get there! No sign-ups, direct download link. It is intended for first-time #UVM learners Happy New Year 2021!
  4. What is the difference between "uvm sequence library" and "virtual sequence" ? Are these same in usage or different ?
  5. I am trying to verify 8 bit RW registers and in some of the registers 4 bits are RESERVED lets say [3:0] . My bit bash sequence tries to write in these constant bit and flags me a mismatch error in the DUT and Mirrored Value. How do i stop my bit bash sequence from checking these RESERVED bits of a register. Thanks for your help
  6. To All Design and DV Engineers! Xilinx Vivado 2020.1 Supports UVM 1.2 and many features of Systemverliog. It supports the same in WebPack (Freeware) Version. There are some limitations on side of assertion cover properties but rest it compile complete SV and UVM including constraints and randomization. Learning UVM without hands-on is difficult. I believe this is opportunity for students, engineers and hobbyists to skill up without relying on paid or online tools as now you can run UVM on your system. For getting started, even though there are many UVM generators, I believe the starters need simple easy to use UVM generator tool. I found the ones available online like Easier UVM or UVMF quite difficult to use and even interact with. I developed a open-source tool "tbengy" to generate a UVM TB and Makefile that will readily get you started and will run on Vivado Simulator. You can read the instructions on https://github.com/prasadp4009/tbengy Hope it helps you all!
  7. Hello All, Please tell me the difference between transaction class and uvm_sequence_item class? Please provide me the clarity on the get_sequence_id method in uvm_sequence_item class Please provide me the clarity on the accept_tr , end_tr, start_tr in uvm_transaction class
  8. Hi, I know this will sound weird, but I will ask anyway :D I have recently completed my first ASIC design(Front end and functional verification). Although I used some SystemVerilog constructs like functions and tasks and some other stuff, but really I verified whole digital part without UVM. My question is: What are the advantages of UVM, and why UVM is needed in the first place, as it seems that tasks and functions can verify any design(it seems only, but I am not so much experienced). Will learned members shed some light on it? Thanks in advance and best wishes in fight against Corona
  9. I am new to UVM and SystemVerilog. For an effective debugging, I wanted to log my transactions coming from the DUT to the monitor into a text file. Since monitor converts into the transaction format, it becomes easy to log the transactions from monitor but I could not find a workaround to do this task. Can someone help with a solution to this problem? Currently, i am using the AHB protocol and I need to keep track of those AHB transactions coming from the DUT. I need to record the address, Read/Write, count, Data to be read/written and time stamps.
  10. Hi Team , import uvm_pkg::*; class hello extends uvm_transaction; rand bit [31:0]b1; rand bit [31:0]b2; `uvm_object_utils_begin(hello) `uvm_field_int(b1, UVM_PACK) `uvm_field_int(b2, UVM_PACK) `uvm_object_utils_end function new(string name = ""); super.new(name); endfunction endclass typedef struct {rand int s; rand int s3;}ss; class par extends uvm_transaction; function new(string name = ""); super.new(name); endfunction rand bit [31:0]s1; rand bit [31:0]s2; ss se; rand hello h1; endclass class par1 extends par; `uvm_object_utils_begin(par1) `uvm_field_int(s2, UVM_PACK) `uvm_field_int(s1, UVM_PACK) `uvm_field_int(se.s, UVM_PACK) `uvm_field_object(h1, UVM_PACK) `uvm_field_int(h1.b1, UVM_PACK) `uvm_field_int(h1.b2, UVM_PACK) `uvm_object_utils_end function new(string name = ""); super.new(name); endfunction endclass module top; par1 p; bit [7:0]que[]; initial begin p = par1::type_id::create("p"); p.randomize(); p.pack_bytes(que); //p.s1 = 3; p.s2 = 4; $display("%h, %h", p.s1, p.s2); //que = {p}; $display("%p", que); //$display("%p", p); //que = p; //que = {<<8{new(p)}}; end endmodule I want to pack in form of bits in below format que = {<<8{p.s2, p.s1, p.se.s, h1.b1, b2}} How do i achieve this..?? // que = {<<8{p.s2, p.s1, p.se.s}} //this one is working using uvm field macros. but when i add h1.b1 and h1.b2 which are sub class variables it is not working. How do i acheive this.?
  11. Hi, How to handle memories wide 8 bits in my register model when register map is built with 32 bits width? Thank you Kristina
  12. In my testbench I have two background sequences (call them S1 and S2) perform register access and a test that has multiple threads ( call them T1 to T7) also performing register access on the same shared bus. T1 through T7 need to lock the sequencer in order to perform multi-cycle transactions on the CPU bus. The scenario is S1 issues a write, resulting in arb_sequence_q.size == 1 and arb_sequence_q[0].request == SEQ_TYPE_REQ in the same simulation tick, T1 through T7 issue lock requests. arb_sequence_q.size() == 8 and arb_sequence_q[0] is still the S1 request S2 issues a read, resulting in arb_sequence_q.size() == 9, arb_sequence_q[8].request == SEQ_TYPE_REQ The CPU driver calls get() and the request at the head of arb_sequence_q (the write from S1) gets popped, resulting in arb_sequence_q.size() == 8 and arb_sequence_q[0:6].request = SEQ_TYPE_LOCK and arb_sequence_q[7].request == SEQ_TYPE_REQ (this is the request from S2). finish_item is called for the S1 request, resulting in grant_queued_locks getting called, pushing all LOCK requests onto the lock_list and leaving only S2 on the arb_sequence_q. arb_sequence_q.size() == 1, arb_sequence_q[0].request = SEQ_TYPE_REQ (this is the S2 request) lock_list.size() == 7 arb_completed.num() == 0 T1 calls write, enqueuing a SEQ_TYPE_REQ on the arb_sequence_q. The arb_sequence_q.size() == 2, arb_sequence_q[0] is S2's request and arb_sequence_q[1] is T1's request. [edit] Here's where the problem hits. Because the lock_list size() > 1, when the consumer (driver) calls get(), the sequencer will cycle through all its requests in its arb_sequence_q until it finds one that is ~is_blocked(). Unfortunately, that function cycles through all sequences in the lock_list regardless of whether the first item in the lock list corresponds to the request being processed. So since we have 7 locks in there, one for each thread, when the driver tries to get a new sequence, T1 will always be blocked by T2:T7. Similarly any request from T1:T7 will get locked out by the others. We've now deadlocked. I believe there is an issue here with the is_blocked() function which should have some form of priority encoding.
  13. Hello, I was wondering if are there any resources (papers, blogs, posts, best practices) about methodologies to implement UVM RAL for "large" designs (>100K registers and 50K rams)? I tried to do some research online but most of the results never cover "large" designs. I have experience using RAL and doing some customisation to make it work in a particular environment (callbacks, maps, defining specialised registers, sequences) but most of them were "little" (1K regs and 100 rams) I'm interested on any information about aspects such as: Reg model re-usability and portability at sub-system and system level environments Performance: How heavy is the register model, since having this much registers may have a huge performance penalty over simulations Dynamic reconfiguration (I know in 1.2 once your model is locked not much can be done) RAM modelling in RAL (since it the uvm_mem is different from uvm_reg) Register Model Partitioning at block level Register Model limitations on real projects usage Implementation of different sized registers and non uniform mapping General RAL limitations Any material or hints on these topics is really appreciated Apologies for the broad question Thanks -R
  14. Hi All, I am a beginner in the field of hardware verification (1.5 yrs experience only). I have done couple of projects in UVM related to IPs such as UART and GPON. Now, i want to take up the next challenging (due to it's huge state space) self project - UVM based verification of a microprocessor. But i am unaware as to how should i begin? I searched the Web and there is so much material that i am totally confused. Can anybody share what should be my approach? How should i begin? Which microprocessor i should chose? From where can i get the DUT processor code? If anyone has implemented such project, could you please share the details. Thanks Krishna
  15. Hi All, I am working in verification. Where i have to generate reg_block for all the IP's using IPXACT. also top level reg_block which instantiates all the IP level register block using IPXACT. But i am not interested in Ports/Businterface/component. Please advise me what is the best method to do it. Thanks Saravanan
  16. I am new to Synopsys VCS. I have been trying to simulate the testbench developed in UVM using VCS in command mode (Linux environment). But, I am not able to get the info displays and the output displays. I am have written the makefile using perl scritps. Can soemeone please tell me where I can find the detail example of using the options in my makefile to run it succesfully while viewing the output displays in command mode
  17. Saw the UVM-SystemC-1.0-beta1 download link, try to install it, but according to the INSTALL file, I can't find "configure" in the package. How could I install it?
  18. I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals?
  19. Hello All, I am working on SystemC-UVM based testbench. I have created UVM based testbench using UVM code generator. Here I am using three different agents in UVM generator which I have defined as a part of the configuration file which was further being provided to UVM code generator to generate test bench skeleton. And here, in of the agent driver, the code snippet is as: // Drive the inputs of the DUT UVM_INFO(this->name(),"Driving transaction:",0); req.print(); // TODO put your code here But when I try to read the value in my test-case, then I see an error as: And this error is observed inside print() function, once I comment the line "req.print()" from the above snippet the error is no more observed and my test-case runs fine.
  20. Hi , To whom may correspond I think there is some kind of error in the UVM 1.1d register model. I have been experimenting with the UVM register model and i have seen the following code in uvm_reg_map.svh task uvm_reg_map::do_bus_write (uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter); uvm_reg_addr_t addrs[$]; uvm_reg_map system_map = get_root_map(); int unsigned bus_width = get_n_bytes(); uvm_reg_byte_en_t byte_en = -1; uvm_reg_map_info map_info; int n_bits; int lsb; int skip; int unsigned curr_byte; int n_access_extra, n_access; int n_bits_init; Xget_bus_infoX(rw, map_info, n_bits_init, lsb, skip); addrs=map_info.addr; // if a memory, adjust addresses based on offset if (rw.element_kind == UVM_MEM) foreach (addrs[i]) addrs[i] = addrs[i] + map_info.mem_range.stride * rw.offset; foreach (rw.value[val_idx]) begin: foreach_value uvm_reg_data_t value = rw.value[val_idx]; /* calculate byte_enables */ if (rw.element_kind == UVM_FIELD) begin int temp_be; int idx; n_access_extra = lsb%(bus_width*8); n_access = n_access_extra + n_bits_init; temp_be = n_access_extra; value = value << n_access_extra; while(temp_be >= 8) begin byte_en[idx++] = 0; temp_be -= 8; end temp_be += n_bits_init; while(temp_be > 0) begin byte_en[idx++] = 1; temp_be -= 8; end byte_en &= (1<<idx)-1; for (int i=0; i<skip; i++) void'(addrs.pop_front()); while (addrs.size() > (n_bits_init/(bus_width*8) + 1)) void'(addrs.pop_back()); end curr_byte=0; n_bits= n_bits_init; The code continues but the interesting part is already there. Lets assume we have a register with 4 bytes and 1byte per address granularity (byte_addressing). Now, we do a FIELD access of 8bits length (the first byte of a register). The field is configured "individual_accessible, so UVM should only access that FIELD. The reg2bus should generate that byte request to be written. In other words, the vector "addrs" should have only one byte address. Going to the code, i see that initially the addrs has the 4 address ( the whole register) and when it comes to the "if (rw.element_kind == UVM_FIELD) begin" and it will pop_back()/remove all the exceeding bytes that doesn't need to complete "n_bits_init" of the field access. The problem is here: UVM has //while (addrs.size() > (n_bits_init/(bus_width*8) + 1)) and i think it should be while (addrs.size() > ((n_bits_init-1)/(bus_width*8) + 1)) //ejonalv possible error in UVM? check That is because in case we want to write 8 bits, it will calculate 8/8+1=2 address in the UVM version, but in fact it should require only 1 address. This is of course applicable for the READ variation. Did i misunderstand something? It is very hard to go through the register model without proper documentation in the code. I am looking forward your answer Best Regards Jonathan
  21. Hi, The purpose of this discussion is to understand different possibilities by which the simulation performance, memory usage can be increased. Scoreboard as we understand needs the data/packets/frames etc to be stored/buffered to do a comparison with the actual data out. This works out fine when we have small sized array ranging from few bytes to few thousands of bytes.. However imagine, if we have 100 thousands of bytes and above and there is a need to store them and lets say multiple of such lanes/flows , then this would take a hit on the simulation performance. And this gets worse if we have to reuse and port it to a subsytem/chip level simulations.. With this as the background, i am looking at alternate approach for scoreboards.. In a way is possible avoid scoreboard and check the data as it comes without the need to store the expected/input data. Approach that can be thought of : 1. Generating incremental data pattern and check at the output .. (Comes again with issues like aliasing etc.. and hence need to have longer patterns.) 2. Generation of PRBS stream as the payload of the frame.. and then have a PRBS checker at the output.. and see it remains locked.. (Debug would get worse with this.. if there is a mismatch) 3. Having a byte scoreboard.. something like that.. (Not sure how feasible this is). There are many challenges even with these approach.. I am just wondering if someone has already experienced such cases and what kind of challenges are thrown out.. Appreciate any input on this. Regards, svuvmuser !
  22. Hi why does phase.find_by_name(.name(uvm_main_phase::get().get_name()), .stay_in_scope(0)); from run_phase and uvm_pkg::uvm_phase run_phase = phase.find_by_name(.name(uvm_run_phase::get().get_name()), .stay_in_scope(0)); from main_phase return null. Is this intentional? I have created a sample example to check, or you can use the attached file as well. https://www.edaplayground.com/x/5Py7 test.svh
  23. Hi, I have a doubt regarding an interface "X" being defined as : Driver code of the VIP: *********************************************** protected virtual X ChipIf; function void connect phase(uvm_phase phase); Y vif_container; super.connect_phase(phase); // Assigning virtual interface assert(uvm_config_object::get(this, "","V_IF_CHIP", temp)); $cast(vif_container, temp); ChipIf = vif_container.get_v_if(); endfunction : connect_phase ********************************************************** From the tb_top of the SoC , where the above VIP pkg is imported along with uvm pkg:*,please let me know how can I "set" the virtual ChipIf?
  24. The VCS implementation of uvm_reg_bit_bash_seq UVM register bit bash sequence performs a model.reset() in the sequence body, before starting the core do_block() task. Due to this reset, any configurations made to the DUT before starting the bit bash sequence is lost in the mirror model, while the DUT still has the configuration intact. This is causing failures during the bit-bash process, resulting in a test fail. There is no knob to override the reset functionality, nor can I extend the sequence and bypass the reset. Any thoughts on this? Any work around for this? ~Chethan
  25. I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!
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