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  1. In my earlier UVM days I ran into this confusing error message a number of times. I just hit it again, so am posting my solution here, to share and to help myself rediscover when it is time. Error (running IUS 13.1): uvm_analysis_imp_my_snoop #( xyz_trans, my_scoreboard) my_snoop_port; | ncvlog: *E,EXPENC (/user/goblin_dev/tb/my_scoreboard.svh,60|50): Expecting the keyword 'endclass'. Below is the pseudo code w/o the error. In converting the real code to pseudo code (to make it more succinct and sterilized), I do not believe I created any inconsistencie
  2. I've run into the following issue using the built-in UVM register tests. The built-in UVM register tests (seem to) start R/W-ing immediately after top-level reset is released. This was fine, initially. See attached image "Capture". We now have some delay between the release of top-level reset and the actual reset going to the register block. This is resulting in a read occurring before reset to the rtl regblock is released, and causes the test to hang. See attached image "Capture2". Without modifying the built-in register tests/sequences, how would anyone suggest that we cleanly
  3. Not sure do you have similar problem? I have a problem in handling the reset value in RAL. f the reset value of a field in the register is don't care, what can I do for it? Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked. Do you guys think it is a feasible way? Thanks.
  4. One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad p
  5. Doulos will be running a webinar on Friday 26th April "The Finer Points of UVM Sequences". Presented by John Aynsley, Doulos CTO Register here! http://www.doulos.com/content/events/easierUVM_The_Finer_Points.php
  6. Hi I am new to UVM. Can any one provide the sample example for using uvm_post_main_phase? Thanks, Ravi
  7. Dear SystemVerilog/UVM User, I've setup a SystemVerilog Meetup in Silicon Valley for people who are interested in hashing over problems they're having or learning new features in a group setting. http://www.meetup.com/SystemVerilog-Social-Club-Silicon-Valley/ I look forward to seeing you there. all the best, Linc Jepson
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