Jump to content

Search the Community

Showing results for tags 'SystemC'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM 2017 - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus 1.0
    • Portable Stimulus Pre-Release Discussion
  • IP Security
    • IP Security Assurance Whitepaper Discussion
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL












Found 141 results

  1. Hi All , I am new to SytemC and I am designing a FIFO . When I run the make file I am getting an error " no match for ‘operator=’ in ‘((sync_fifo*)this)->sync_fifo::wptr = 0’ " . I guess this has do with the sensitivity list of wptr and rptr but I am not sure how to fix it.I have highlighted the lines where I am getting error . It will be really helpful if someone could explain this . Thank you #include <systemc.h> SC_MODULE (sync_fifo){ sc_in_clk clk; sc_in<bool> rst; sc_in<bool> rd_wr; sc_out<bool> full; sc_out<bool> empty; sc_in < sc_uint<8> > data_in; sc_in < sc_uint<4> > wptr; sc_in < sc_uint <4> > rptr; sc_out < sc_uint<8> > data_out; sc_uint<8> ram_data[256]; void read_write() { if(rst == 1) { wptr=0;rptr=0;data_out=0; } else if(rd_wr == 1 && !full) { ram_data[wptr.read()]=data_in; wptr=wptr+1; } else if(rd_wr == 0 && !full) { data_out=ram_data[rptr.read()]; rptr=rptr+1; } } void emp_ful(){ if(rst == 1) { full=0; empty=0; } else { if(wptr == rptr ) { empty=1; } else if((wptr - rptr) == 15) { full=1; } else { full=empty=0; } } } SC_CTOR(sync_fifo) { SC_METHOD(read_write); sensitive << clk.pos() << rst ; sensitive << wptr ; sensitive << rptr; SC_METHOD(emp_ful); sensitive << clk.pos() << rst ; sensitive << wptr ; sensitive << rptr ; } };
  2. Hi everyone, Recently, I am studying systemc and have a problem on semaphore channel. Actually, I found an example of semaphore channel on asic world (http://www.asic-world.com/systemc/channels3.html). This example provides 3 processes (SC_CTHREAD): bus_semaphore(), do_read() and do_write(). like below, ------------------------------------------------------------------------------------------------------- #include <systemc.h> SC_MODULE (sc_semaphore_example) { sc_in<bool> clock; sc_semaphore bus; int cnt; void bus_semaphore() { while (true) { wait(); cout << "@" << sc_time_stamp() <<" Check if semaphore is 0 " << endl; if (bus.get_value() == 0) { cout << "@" << sc_time_stamp() <<" Posting 2 to semaphore " << endl; bus.post(); bus.post(); if (cnt >= 3) { sc_stop(); // sc_stop triggers end of simulation } cnt ++; } } } void do_read() { while (true) { wait(); cout << "@" << sc_time_stamp() <<" Checking semaphore for intance 0"<<endl; // Check if semaphore is available if (bus.trywait() != -1) { cout << "@" << sc_time_stamp() <<" Got semaphore for intance 0"<<endl; wait(2); } } } void do_write() { while (true) { wait(); cout << "@" << sc_time_stamp() <<" Checking semaphore for intance 1"<<endl; // Wait till semaphore is available bus.wait(); cout << "@" << sc_time_stamp() <<" Got semaphore for intance 1"<<endl; wait(3); } } SC_CTOR(sc_semaphore_example) : bus(0){ cnt = 0; SC_CTHREAD(do_read,clock.pos()); SC_CTHREAD(do_write,clock.pos()); SC_CTHREAD(bus_semaphore,clock.pos()); } }; int sc_main (int argc, char* argv[]) { sc_clock clock ("my_clock",1,0.5); sc_semaphore_example object("semaphore"); object.clock (clock.signal()); sc_start(0); // First time called will init schedular sc_start(); // Run the simulation till sc_stop is encountered return 0;// Terminate simulation } ===================== simulation result given ==================== @1 ns Check if semaphore is 0 @1 ns Posting 2 to semaphore @1 ns Checking semaphore for intance 1 @1 ns Got semaphore for intance 1 @1 ns Checking semaphore for intance 0 @1 ns Got semaphore for intance 0 @2 ns Check if semaphore is 0 @2 ns Posting 2 to semaphore @3 ns Check if semaphore is 0 @4 ns Check if semaphore is 0 @4 ns Checking semaphore for intance 0 @4 ns Got semaphore for intance 0 @5 ns Check if semaphore is 0 @5 ns Checking semaphore for intance 1 @5 ns Got semaphore for intance 1 @6 ns Check if semaphore is 0 @6 ns Posting 2 to semaphore @7 ns Check if semaphore is 0 @7 ns Checking semaphore for intance 0 @7 ns Got semaphore for intance 0 @8 ns Check if semaphore is 0 @9 ns Check if semaphore is 0 @9 ns Checking semaphore for intance 1 @9 ns Got semaphore for intance 1 @10 ns Check if semaphore is 0 @10 ns Posting 2 to semaphore @10 ns Checking semaphore for intance 0 @10 ns Got semaphore for intance 0 --------------------------------------------------------------------------------------------------------- There might be a problem about the former two threads. At the first 1ns for this example, the first process bus_semaphore() works and can print out all of the two lines like "@1 ns ....". At the same time in this thread then, the semaphore value (bus) changes into 2 (bus.post()). Then this thread will wait for the next clock posedge. So far everything is good. For the second process, do_read(), also at the 1ns, the first "@" line can be printed out normally, but then what about the expression trywait() in the next if-statement? The first and second process should start to work at the same time (all have wait()at the beginning), that is to say we cannot determine whether the trywait() (in the second process) executes before or after the bus.post() statement (in the first process), so we don't know if the second "@" line of the second process will be printed out. But the simulation result shows that the trywait() will execute after the bus.post() executes such that the second "@..." statement in the second process will be printed out. My question is how can I be sure that the trywait() will execute after the bus.post()'s execution? Shouldn't they execute simultaneously? Thanks a lot! Wayne
  3. Hello everybody, I would like to know if AMS and SystemC have two different schedulers. If yes then how do they interact? Moreover i would like to ask how many extensions does SystemC has? Thanks in advance
  4. Hi Experts, How do I pass "Maps" within constructors while using a SystemC struct? I want to instantiate this module 4 times and use 4 different maps for each instance. struct Detector: sc_module { SC_CTOR(Detector) { for (int i = 0 ; i<10 ; i++) { in_map= map[0]; // in_map has been declared as private & map is passed on through the constructor } } Thankyou in advance!
  5. Hello all, I'm simulating MOESI protocol for L1 caches in SystemC. I'm getting different results for the same source code when running in SystemC 2.3.0 and SystemC 2.3.1 versions in different machines. Could anyone kindly pass some light on this topic? Machine1: Linux 3.13, Ubuntu 14.04, SystemC 2.3.1, Intel Pentium Dual Core processor. Output - Machine 1: CPU Reads RHit RMiss Writes WHit WMiss Hitrate 0 6 0 6 4 0 4 0.000000 1 34 0 34 22 0 22 0.000000 2 35 0 35 43 0 43 0.000000 3 39 2 37 46 2 44 4.705882 4 36 0 36 55 0 55 0.000000 5 52 0 52 47 0 47 0.000000 6 48 3 45 51 2 49 5.050505 7 42 1 41 55 5 50 6.185567 Total: 292 6 286 323 9 314 15 Avg: 36 0 35 40 1 39 1 2. Main memory access rates Bus had 286 reads and 1 upgrades and 314 readX. A total of 601 accesses. 3. Average time for bus acquisition There were 50 waits for the bus. Average waiting time per access: 0.083195 cycles. 4. There were 1 Cache to Cache transfers 5. Total execution time is 10204 ns, Avg per-mem-access time is 16.978369 ns 6. Probe Read: 5, Probe ReadX: 7 Machine 2: Linux 3.13, Ubuntu 14.04, SystemC 2.3.0, Intel i7 Quad Core processor. Output - Machine 2: CPU Reads RHit RMiss Writes WHit WMiss Hitrate 0 6 0 6 4 0 4 0.000000 1 34 0 34 22 0 22 0.000000 2 35 0 35 43 0 43 0.000000 3 39 2 37 46 2 44 4.705882 4 36 0 36 55 0 55 0.000000 5 52 0 52 47 0 47 0.000000 6 48 3 45 51 2 49 5.050505 7 42 1 41 55 5 50 6.185567 2. Main memory access rates Bus had 286 reads and 0 upgrades and 314 readX. A total of 600 accesses. 3. Average time for bus acquisition There were 51 waits for the bus. Average waiting time per access: 0.085000 cycles. 4. There were 0 Cache to Cache transfers 5. Total execu tion time is 10204 ns, Avg per-mem-access time is 17.006667 ns 6. Probe Read: 1 , Probe ReadX: 0 Does the version 2.3.0 and 2.3.1 are the reason for the inconsistent result? Source code and steps to run the simulation can be found here. Thanks, Tamilselvan Shanmugam.
  6. Hello Accellera Forum, I'm trying to execute the IP-XACT example of the Leon2 on the accellera page. I'm using systemc2.3.1 on windows8 with cygwin gcc 4.8.3. I try to run the makefile in the directory TLM2, but I´m getting following error: Makefile:130: recipe for target '../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/tlmreg_Leon2_uart.o' failed make: [../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/tlmreg_Leon2_uart.o] Error 127 (ignored) g -m32 -O3 -fpermissive -DVERBOSE_GLOBAL -Wno-deprecated -DSC_INCLUDE_DYNAMIC_PROCESSES -I/cygdrive/c/systemc-2.3.1/include -I/cygdrive/c/systemc-2.3.1/include/tlm -I/include -I/devkit/tlm/include -I/devkit/tlm_message/include -I/devkit/tlm_utilities/include -I/protocol/tlm_tac/include -I../../spiritconsortium.org/Leon2TLM/PV -I../../spiritconsortium.org/Leon2TLM/ahbbus/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/ahbram/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/apbmst/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/apbbus/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/cgu/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/rgu/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/dma/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/irqctrl/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/processor/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/timers/1.4/tlmsrc -I../../spiritconsortium.org/Leon2TLM/scmlAdaptor/1.0/tlmsrc -I../../spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc -I../../spiritconsortium.org/Leon2TLM/serial_device/1.0/tlmsrc -I../../spiritconsortium.org/Leon2TLM/pv2tac/1.0/tlmsrc -I../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/include -I../../spiritconsortium.org/Leon2TLM/SystemTLM2/apbSubSystem/tlmsrc -I../../spiritconsortium.org/Leon2TLM/SystemTLM2/Leon2Platform/tlmsrc -c ../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/user_specific_Leon2_uart.cc -o ../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/user_specific_Leon2_uart.o make: g: Kommando nicht gefunden // Command not found Makefile:130: recipe for target '../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/user_specific_Leon2_uart.o' failed make: [../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/user_specific_Leon2_uart.o] Error 127 (ignored) m32 -o SystemTLM2 SystemTLM2.o bool2sclv.o ../../spiritconsortium.org/Leon2TLM/processor/1.4/tlmsrc/processor.o ../../spiritconsortium.org/Leon2TLM/ahbram/1.4/tlmsrc/ahbram.o ../../spiritconsortium.org/Leon2TLM/dma/1.4/tlmsrc/dma.o ../../spiritconsortium.org/Leon2TLM/cgu/1.4/tlmsrc/cgu.o ../../spiritconsortium.org/Leon2TLM/rgu/1.4/tlmsrc/rgu.o ../../spiritconsortium.org/Leon2TLM/timers/1.4/tlmsrc/timers.o ../../spiritconsortium.org/Leon2TLM/irqctrl/1.4/tlmsrc/irqctrl.o ../../spiritconsortium.org/Leon2TLM/scmlAdaptor/1.0/tlmsrc/scmladaptor.o ../../spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart.o ../../spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart_interrupt_handler.o ../../spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart_register_bank.o ../../spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart_serial_tx_rx.o ../../spiritconsortium.org/Leon2TLM/pv2tac/1.0/tlmsrc/pv2tac.o ../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/Leon2_uart.o ../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/tlmreg_Leon2_uart.o ../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/user_specific_Leon2_uart.o -L/cygdrive/c/systemc-2.3.1/lib- -L/lib- -lsystemc -lModelingObjects /tac_metadata.o /tlm_*.o /bin/sh: m32: Kommando nicht gefunden. // Command not found Makefile:133: recipe for target 'SystemTLM2' failed make: [SystemTLM2] Error 127 (ignored) Could you please help me to get this example running. All other examples in systemc are running perfectly. Thanks, Ralph
  7. Hi Experts, 1.I have seen that Offsets of a Slave Module is described in the Memory Maps in Component Description. Is it possible to describe Offsets in the top design? The motive is to repeat various instances of a Slave Component in a design, each slave instance having a different Offset. 2. Also, I have a SystemC architecture in which I instantiate the same bus several times. But I connect each bus instance with a different number of modules. This is because the bus possesses MultiPassthrough Sockets. How can I reproduce it in IP-XACT? Should I have a custom Component for each bus instance(with separate BusDef and AbsDef ?) as each instance will have a different number of bus interfaces? How can it be done? Looking forward for your response! Thanks in advance, Venkatesh
  8. I have used Modelsim to compare simulation results between a C model encapsulated in SystemC to its VHDL implementation, mostly with a GUI, for hardware verification. I am trying to see how SystemC can be used for Software validation and/or regression testing using a SystemC testbench that has software modules, SystemC models, and VHDL HW modules when fidelity is needed. I am assuming the open-source SystemC simulator does not support VHDL natively so a VHDL simulator would be needed like modelsim. What is the best way to use the SystemC open source simulation to make calls to a VHDL simulator like modelsim while reducing the license usage of modelsim? Can you share your experience and lessons learned regarding mixed language sims? Thanks Paul
  9. I have a question which probably is quite stupid. I developed a Software in the Loop framework in SytemC. This framework is supposed to call in specific discrete time instants some modules to execute. For instance suppose we have module A and B. Module A has to be executed every 10 ms and Module B every 20 ms. The execution order has to be first A and then B when both modules have to be executed. I am able to do that by having a coordinator module triggered by a clock of 10 ms. Every module ( module A, B and scheduler) are related with an event. Module A and B they look like this: while(1){ Wait(ev_mod_i) { ... trigger_ev_coordinator }} The coordinator which knows the frequency of each module will notify the correct event to trigger the corresponding module. So for instance for t=10ms the coordinator will be triggered by the clock and it will trigger event_mod_A. Then for t=20ms it will trigger event_mod_A, after module A is finished coordinator will trigger event_mod_B. After module B is also finished, the coordinator will wait for the next clock tick e.t.c Now i would like to insert an AMS model into my system. The desired MoC is continuous TDF. However I can't use statements like event.notify(zerotime) or wait(ev_i) in TDF according to the AMS manual. Moreover TDF modules include a time step by which they are executed. This is something that is not fully desired because i can't find a way to control the TDF modules. Could you please give me any ideas on how I can embed a TDF model into a SystemC framework and at the same time to be able to control when the model has to be executed for a specific clock tick? Probably by doing this I am ruining the whole concept of continuous TDF MoC. If this is right do you have any alternative ideas? Thanks in advance.
  10. Hello, I have a SystemC program encapsulated into a C++ class allowing to interact with a SystemC model. In order to easily call that program from a scripting language, I would like to generate a shared-library containing all my SystemC program and the SystemC library. Is it different from generating a classical C/C++ shared-library? How can you deal with the sc_main required by the SystemC? Can you point me to some documentation about that topic, I didn't find anything about it for SystemC on the internet... Thank you! Regards! J-B
  11. Hello, I am using systemC-2.3.1 which I think has started supporting native windows(x64) build. I have build the library of systemC using the msvc solution file in visual C++ express 2010. The library is generated under x64/Release directory and I didn't get any build error. But while linking this library with my application it throws an error message as follow: systemc.lib<sc_time.obj> : fatal error LNK1112: module machine type 'x64' conflicts with target machine type 'x86'. I am compiling my application with visual studio command prompt. Am I missing here something ?
  12. Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog
  13. I am trying to use an sc_vector of modules with a custom creator to pass constructor arguments. It seems to work and run through the entire program, but at exit causes a segfault. GDB shows that this is due to to sc_vector calling the destructor of the module. I have no dynamically-allocated memory or pointers in the module. Here's the overview: outside of sc_main (global -- but I also tried inside of sc_main): -------------------------- struct create_mod { unsigned int m_arg1; unsigned int m_arg2; create_mod(unsigned int arg1, unsigned int arg2) : m_arg1(arg1), m_arg2(arg2) {} mod* operator()(const char* name, size_t) { return new mod(name, m_arg1, m_arg2); } }; Inside sc_main: --------------------------- unsigned int num_of_mods = 8; unsigned int args1 = 5, args2 = 4; sc_vector<mod> vec_mod("mods"); vec_mod.init(num_of_mods, create_mod(args1, args2)); // ... use vec_mod, bind ports, etc ... return 0; So the program runs, then segfaults at the end with "core dumped". GDB results: Backtracing shows: Note the bit in red. Also note that line 334 is the closing brace of sc_main. Also: As I said, I have no dynamically-allocated memory in the class. I have tried an empty destructor (as well as = default since I'm using C++11) but got the same result. Any ideas? Thanks in advance.
  14. Good day. I am new to SystemC and TLM. Here I am implementing producer-consumer model with a bus and memory model. The synchronization between producer-consumer is done using semaphore. I add DMI feature to the simulation. So the idea is to give producer direct access to the memory region. The same goes for the consumer. What I expect from doing this is to gain faster simulation time. However, at some point of my experiment it shows that using DMI takes longer simulation time. Is this normal to happen? Or I might implement the DMI in the wrong way? Thank you. Best regards, Li.
  15. I need to develop a SystemC model for a new (nonexisting) bus architecture, change it whenever needed and investigate its performance with every change. I do not know how to start on that, there is no tutorials or books that focus on using systemC in practical projects, all that's available is on the language itself. how do I approach this problem? how to start?
  16. Hi All: Get to implement a timer module in SytemC-TLM. And it is at LT level. The Time used for interrupt generation is from sc_time_stamp. My current implementation is using TLM payload event queue, which means the timer caculates the expected wait time for the request and do "notify(x ns)" for the payload event queue. Which the drawback is: 1.When I add the cancel function for a ongoing time request, I can't delete the "time request" from the event queue. I do a workaround like saving some tags when the timeout happened to achieve the "cancel" 2.When I add a stop function for the timer, I also need a tag and did lots of workaround in order to fullfil the stop/re-start function. So, is there any foward way to do this? If i do my own queues instead of using Payload event queue(But I guess I still need to use notify(x ns) in some way), may I somehow delete a ongoing requests? Thanks BR
  17. Hi everybody, I have a simple question (not so sure if the answer is simple too). Is it possible to "pause"/"halt" the simulation temporarily? It would be useful for me in two scenarios: Whenever the simulation reaches a specified point in the code. Just like a breakpoint, but not having the need to use a debugger. So whenever the user presses a key, the simulation goes on. Whenever the simulation reaches a point, where a user needs to send an input. It is similar to the previous one, but the here the user would need to enter an input (int, double, string, etc.). I understand that this may be harder for the simulation. So, any ideas? Is there any sc_pause? I know that there is a sc_halt, but it looks like it works only with threads, which would not be suitable to be called from an AMS module. Thanks a lot! ;-)
  18. I have a platform for native simulation, composed with sc_main.cpp, native_wrapper.cpp, native_wrapper.h, hardware.... I have to implement another CPU but I didn't find a method to make this. Because extern "C" is needed since the software is compiled in C and is linked against native_wrapper.cpp, which is compiled in C++, for this, we call methods of soft in a this manner, using “NativeWrapper::get_instance()->method_name()” below you can see code of sc_main.cpp, native_wrapper.cpp and native_wrapper.h.Thanks for your help code for native_wrapper.h #include "ensitlm.h" #include "native_wrapper.h" /* extern "C" is needed since the software is compiled in C and * is linked against native_wrapper.cpp, which is compiled in C++. */ extern "C" int __start(); extern "C" void __interrupt(); extern "C" void write_mem(uint32_t addr, uint32_t data) { //abort(); // TODO NativeWrapper::get_instance()->write_mem(addr, data); } extern "C" unsigned int read_mem(uint32_t addr) { //abort(); // TODO return NativeWrapper::get_instance()->read_mem(addr); } extern "C" void cpu_relax() { //abort(); // TODO NativeWrapper::get_instance()->cpu_relax(); } extern "C" void wait_for_irq() { //abort(); // TODO NativeWrapper::get_instance()->wait_for_irq(); } NativeWrapper * NativeWrapper::get_instance() { static NativeWrapper * instance = NULL; if (!instance) instance = new NativeWrapper("native_wrapper"); return instance; } NativeWrapper::NativeWrapper(sc_core::sc_module_name name) : sc_module(name), irq("irq") { SC_THREAD(compute); SC_METHOD(interrupt_handler_internal); sensitive << irq ; dont_initialize(); } void NativeWrapper::write_mem(unsigned int addr, unsigned int data) { tlm::tlm_response_status stat = socket.write(addr, data); } unsigned int NativeWrapper::read_mem(unsigned int addr) { //abort(); // TODO uint32_t localbuf; tlm::tlm_response_status stat = socket.read(addr,localbuf); return localbuf; } void NativeWrapper::cpu_relax() { //abort(); // TODO wait(1000, sc_core::SC_MS); /* temps arbitraire */ } void NativeWrapper::wait_for_irq() { if (!interrupt) wait(interrupt_event); interrupt = false; } void NativeWrapper::compute() { //abort(); // TODO __start(); } void NativeWrapper::interrupt_handler_internal() { interrupt = true; interrupt_event.notify(); __interrupt(); } and native_wrapper.h : #ifndef NATIVEWRAPPER_H #define NATIVEWRAPPER_H #ifndef ENSITLM_H #error Please include file "ensitlm.h" #endif SC_MODULE(NativeWrapper) { ensitlm::initiator_socket<NativeWrapper> socket; sc_core::sc_in<bool> irq; private: SC_CTOR(NativeWrapper); public: /* We use a singleton here. This is a limitation since it doesn't allow multiple NativeWrapper instances (multiple CPU in the platform), but it considerably reduces the complexity of Makefiles, hal.h, ... */ static NativeWrapper * get_instance(); void write_mem(unsigned int addr, unsigned int data); unsigned int read_mem(unsigned int addr); void cpu_relax(); void wait_for_irq(); void compute(); void interrupt_handler_internal(); bool interrupt; sc_core::sc_event interrupt_event; }; #endif sc_main.cpp #include "ensitlm.h" #include "native_wrapper.h" #include "memory.h" #include "bus.h" #include "timer.h" #include "vga.h" #include "intc.h" #include "gpio.h" int sc_main(int, char**) { NativeWrapper& cpu = *NativeWrapper::get_instance(); Memory memory("Memory", 0x00100000); Bus bus("bus"); TIMER timer("timer", sc_core::sc_time(20, sc_core::SC_NS)); Vga vga("vga"); Intc intc("intc"); Gpio gpio("gpio"); ......
  19. Hi again! Maybe this is too obvious, but I've been wonderin for a while now and never found the answer (and dared to ask for it ). Is it possible to directly pass whatever comes from an tdf_in port to a tdf_out port? Not only that, is it possible to do it in a sc_module instead of a sca_module? For a better explanation I'll leave a piece of code. Let's say I have: #include <systemc-ams> class some_module : public sc_core::sc_module { public: sca_tdf::sca_in<int> in; sca_tdf::sca_out<int> out; some_module(sc_core::sc_module_name nm); }; Until now I was adding an object, let's call it "tdf_some": #include <systemc-ams> class tdf_some_module : public sca_tdf::sca_module { public: sca_tdf::sca_in<int> in; sca_tdf::sca_out<int> out; tdf_some_module(sc_core::sc_module_name nm) {} void processing() { out.write( in.read() ); } }; Then, in the previous class I would change to: #include <systemc-ams> class some_module : public sc_core::sc_module { public: sca_tdf::sca_in<int> in; sca_tdf::sca_out<int> out; // Add new TDF module tdf_some *ts; some_module(sc_core::sc_module_name nm) { // Instantiate and bind ports ts = new tdf_some("ts"); ts->in(in); ts->out(out); } }; Looks like a very simple question (and I hope so), but I still haven't been able to solve it. Any ideas? Thanks
  20. Hi, I am getting errors like below: Trace ERROR: No traces can be added once simulation has started. To add traces, create a new vcd trace file. Code of memory.cpp corresponding to error: Memory::Memory(sc_core::sc_module_name name, unsigned int size) : sc_module(name), m_size(size) { tf = sc_core::sc_create_vcd_trace_file("trace_data1"); // tracing, trace file creation tf->set_time_unit(10, sc_core::SC_US); storage = new ensitlm::data_t[size/sizeof(ensitlm::data_t)]; } // Destructor Memory::~Memory() { // close trace file sc_close_vcd_trace_file(tf); delete [] storage; } // Read transactions tlm::tlm_response_status Memory::read(ensitlm::addr_t a, ensitlm::data_t& d) { // Check if the address is within memory bounds if (a >= m_size) { sleep(5); return tlm::TLM_ADDRESS_ERROR_RESPONSE; } else { d = storage[a/sizeof(ensitlm::data_t)]; sc_trace(tf, d ,"d"); return tlm::TLM_OK_RESPONSE; } } // Write transactions tlm::tlm_response_status Memory::write(ensitlm::addr_t a, ensitlm::data_t d) { // Check if the address is within memory bounds if (a >= m_size) { sleep(5); return tlm::TLM_ADDRESS_ERROR_RESPONSE; } else { storage[a/sizeof(ensitlm::data_t)] = d; return tlm::TLM_OK_RESPONSE; } } code of memory.h : SC_MODULE(Memory) { ensitlm::target_socket<Memory> target; sc_core::sc_trace_file *tf; Memory(sc_core::sc_module_name name, unsigned int size); ~Memory(); tlm::tlm_response_status read(ensitlm::addr_t a, ensitlm::data_t& d); tlm::tlm_response_status write(ensitlm::addr_t a, ensitlm::data_t d); private: unsigned int m_size; public: /* The loader must have access to the storage */ ensitlm::data_t* storage; }; #endif Please tell me the reasons behind these errors Regards Hakimelectronics
  21. Hi Can anybody please tell me how to write a transactor for an existing System C model? I can write a systemC model as well as a LT TLM model. But i don't know how to interconnect both of them using ports. Any valuable help would be appreciated. Thanks
  22. We are using TLM to pass transactions from SystemVerilog to SystemC. I have two cases where I am stuck. Actually, it is the same case, but I have two angles to my question. 1) Is it possible to still use a TLM setup, but without a transaction type. (I realize that this is contradictory to the acronym.) A c-model has a debug function which takes no input arguments. So, when the SV testbench runs into a problem, it can call this function in the SystemC/c-model. As all of our connections now are sc_port/sc_export, with TLM, I'd like to stick with that flow if possible, rather than adding DPIs/VPIs/(PLIs) or any other mechanism to communicate between languages. However, since the function has no input arguments, I don't need a transaction type. So, is there a way to do a TLM call without a transaction type? (I suppose I could just use another transaction type and ignore the data.) 2) Imagine the above c-model input function that takes no input arguments. Let's say now that the c-model function takes a single integer as its input. So, now I do have a transaction type, but a very simple one. It seems like overkill, but do I still need to define matching .h and .svh (that extends uvm_sequence_item) transcation types and the related do_pack, do_unpack, etc. routines? It seems like overkill. I suspect that I must, if I want to use TLM. (Given that the answer to this question must be, yes, does anyone out there just use a generic grab-bag transaction type for cases like this?) //my thought of passing a transaction which is just an int in sv tb: uvm_blocking_put_port #(int) sb_debug_call1_to_cmodel; in sc c-model public tlm::tlm_blocking_put_if<sc_int <32>> //or smthg like that Any thoughts? I know I just need to refresh myself on DPIs, but answers to the above question are welcome.
  23. Hi everybody! About my model: Here is two different initiators and one target. Initiators makes b_transport to different sockets. first b_transport of each initiator its "req to transition", second - data transition. Could anybody help me to write synch point? My target should will call some behavioral function when all initiators will make "req to transition". Could anybody helps me to change this code? Please, help me! #define SC_INCLUDE_DYNAMIC_PROCESSES #include <systemc.h> #include <tlm.h> #include <tlm_utils\simple_initiator_socket.h> #include <tlm_utils\simple_target_socket.h> SC_MODULE(Initiator) { tlm_utils::simple_initiator_socket<Initiator> socket; void process() { tlm::tlm_generic_payload *trans = new tlm::tlm_generic_payload; sc_time delay = sc_time(10, SC_NS); for(int i =0 ; i < 100; i++) { cout << "Initiator1: send payload with req to target @ " << sc_time_stamp() << endl; socket->b_transport(*trans, delay); if(trans->is_response_ok()) { cout << "Initiator1: Start transaction. Send data @ " << sc_time_stamp() << endl; trans->set_data_ptr(reinterpret_cast<unsigned char*>(&i)); socket->b_transport(*trans, delay); } } } SC_CTOR(Initiator) { SC_THREAD(process); } }; SC_MODULE(Initiator2) { tlm_utils::simple_initiator_socket<Initiator2> socket; void process() { tlm::tlm_generic_payload *trans = new tlm::tlm_generic_payload; sc_time delay = sc_time(0, SC_NS); for(int i =5 ; i < 100; i++) { cout << "Initiator2: send payload with req to target @ " << sc_time_stamp() << endl; socket->b_transport(*trans, delay); if(trans->is_response_ok()) { cout << "Initiator2: Start transaction. Send data @ " << sc_time_stamp() << endl; trans->set_data_ptr(reinterpret_cast<unsigned char*>(&i)); socket->b_transport(*trans, delay); } } } SC_CTOR(Initiator2) { SC_THREAD(process); } }; SC_MODULE(Target) { tlm_utils::simple_target_socket<Target> socket, socket2; bool dataRecievedI1, dataRecoevedI2; virtual void process1(tlm::tlm_generic_payload &tx, sc_time& dt) { if(!dataRecievedI1) { wait(socket->default_event()); } } virtual void process2(tlm::tlm_generic_payload &tx, sc_time& dt) { if(!dataRecoevedI2) { } } SC_CTOR(Target) { dataRecievedI1 = false; dataRecoevedI2 = false; socket.register_b_transport(this, &Target::process1); socket2.register_b_transport(this, &Target::process2); } }; SC_MODULE(Top) { Initiator *initiator; Initiator2 *initiator2; Target *target; SC_CTOR(Top) { initiator = new Initiator ("initiator"); target = new Target ("target"); initiator2 = new Initiator2("initiator2"); initiator->socket.bind(target->socket); initiator2->socket.bind(target->socket2); } }; int sc_main(int argc, char* argv[]) { Top top("top"); sc_start(); getchar(); return 0; }
  24. Hi everyone, I'm met some problem. In box below you can see my code. struct Some_stuct { int data; float data_f; }; class payload_t { public: unsigned char *data; unsigned lenght; inline friend ostream& operator << ( ostream& os, payload_t const & v ) { os << "(" << v.data << "," << std::boolalpha << "," << v.lenght << ")"; return os; } }; SC_MODULE(tx) { sc_port<sc_fifo_out_if<payload_t> > out_port; void process() { Some_stuct data; payload_t out_data; while(true) { data.data = 5; data.data_f = 6; out_data.data = reinterpret_cast<unsigned char*>(&data); out_data.lenght = sizeof(Some_stuct); out_port->write(out_data); data.data++; data.data_f++; wait(1, SC_NS); } } SC_CTOR(tx) { SC_THREAD(process); } }; SC_MODULE(rx) { sc_port<sc_fifo_in_if<payload_t> > in_port; void process() { int realData = 0; payload_t in_data; while(true) { wait(in_port->data_written_event()); wait(171, SC_NS); in_data = in_port->read(); Some_stuct *val = reinterpret_cast<Some_stuct*>(in_data.data); cout << sc_time_stamp() << " " << val->data << " " << val->data_f << endl; } } SC_CTOR(rx) { SC_THREAD(process); } }; int sc_main(int argc, char* argv[]) { rx rx_i("rx"); tx tx_i("tx"); sc_fifo<payload_t> buf(8); tx_i.out_port(buf); rx_i.in_port(buf); sc_start(); getchar(); return 0; } I'm have two blocks: transmitter and receiver. When we call method write to fifo from transmitter, actually we will send address of our local data. And when i will read from buffer, I will receive address of transmitter local data. But if transmitter works more faster than receiver, my rx block will receive "New" data and sended data will loss. How to solve this problem? I should receive correct data
  25. Hi I'm learning SystemC language and I made a JK flipflop and 8bit counter using 8-JK flipflop there's no problem building project but if I running GTKwave using vcd trace file it cannot show anything. please help me //test.h #include "systemc.h" SC_MODULE(test) { sc_in<bool> clock; sc_out<bool> go; void do_test(); SC_CTOR(test) { SC_CTHREAD(do_test, clock); go.initialize(0); } }; //test.cpp #include "test.h" void test::do_test() { go.write(1); while(true) { wait(1); } } //JK_FlipFlop.h #include "systemc.h" SC_MODULE(JK_FlipFlop) { sc_in<bool> Input_J; sc_in<bool> Input_K; sc_in<bool> Input_clk; sc_out<bool> Output_q1; sc_out<bool> Output_q2; void do_jk(); SC_CTOR(JK_FlipFlop) { SC_METHOD(do_jk); sensitive<< Input_clk.neg() << Input_J << Input_K; Output_q1.initialize(0); Output_q2.initialize(1); } }; //JK_FlipFlop.cpp #include "JK_FlipFlop.h" void JK_FlipFlop::do_jk() { if(Input_J == true && Input_K == false) { Output_q1.write(1); Output_q2.write(0); } else if(Input_J == false && Input_K == true) { Output_q1.write(0); Output_q2.write(1); } else if(Input_J == true && Input_K == true) { Output_q1.write(!Output_q1); Output_q2.write(!Output_q2); } else { Output_q1.write(Output_q1); Output_q2.write(Output_q2); } } //counter.h #include "JK_FlipFlop.h" SC_MODULE(counter) { sc_in<bool> clk, go; sc_out<unsigned char> value; sc_signal<bool> connect1; sc_signal<bool> connect2; sc_signal<bool> connect3; sc_signal<bool> connect4; sc_signal<bool> connect5; sc_signal<bool> connect6; sc_signal<bool> connect7; sc_signal<bool> connect8; sc_signal<bool> no1, no2, no3, no4, no5, no6, no7, no8; JK_FlipFlop *FF1; JK_FlipFlop *FF2; JK_FlipFlop *FF3; JK_FlipFlop *FF4; JK_FlipFlop *FF5; JK_FlipFlop *FF6; JK_FlipFlop *FF7; JK_FlipFlop *FF8; void do_count(); SC_CTOR(counter) { FF1 = new JK_FlipFlop("jk1"); FF2 = new JK_FlipFlop("jk2"); FF3 = new JK_FlipFlop("jk3"); FF4 = new JK_FlipFlop("jk4"); FF5 = new JK_FlipFlop("jk5"); FF6 = new JK_FlipFlop("jk6"); FF7 = new JK_FlipFlop("jk7"); FF8 = new JK_FlipFlop("jk8"); FF1->Input_clk(clk); FF1->Input_J(go); FF1->Input_K(go); FF1->Output_q1(connect1); FF1->Output_q2(no1); FF2->Input_clk(connect1); FF2->Input_J(go); FF2->Input_K(go); FF2->Output_q1(connect2); FF2->Output_q2(no2); FF3->Input_clk(connect2); FF3->Input_J(go); FF3->Input_K(go); FF3->Output_q1(connect3); FF3->Output_q2(no3); FF4->Input_clk(connect3); FF4->Input_J(go); FF4->Input_K(go); FF4->Output_q1(connect4); FF4->Output_q2(no4); FF5->Input_clk(connect4); FF5->Input_J(go); FF5->Input_K(go); FF5->Output_q1(connect5); FF5->Output_q2(no5); FF6->Input_clk(connect5); FF6->Input_J(go); FF6->Input_K(go); FF6->Output_q1(connect6); FF6->Output_q2(no6); FF7->Input_clk(connect6); FF7->Input_J(go); FF7->Input_K(go); FF7->Output_q1(connect7); FF7->Output_q2(no7); FF8->Input_clk(connect7); FF8->Input_J(go); FF8->Input_K(go); FF8->Output_q1(connect8); FF8->Output_q2(no8); SC_METHOD(do_count); sensitive << clk; sensitive << go; } }; //counter.cpp #include "counter.h" void counter::do_count() { unsigned char local_value = 0; local_value |= (FF1->Output_q1)<<0; local_value |= (FF2->Output_q1)<<1; local_value |= (FF3->Output_q1)<<2; local_value |= (FF4->Output_q1)<<3; local_value |= (FF5->Output_q1)<<4; local_value |= (FF6->Output_q1)<<5; local_value |= (FF7->Output_q1)<<6; local_value |= (FF8->Output_q1)<<7; value.write(local_value); } //main.cpp #include "counter.h" #include "test.h" int sc_main(int argc, char* argv[]) { sc_signal<unsigned char> Value; sc_signal<bool> Go; sc_clock CLK("clock", 50, SC_NS); counter COUNTER("ccc"); COUNTER.clk(CLK); COUNTER.go(Go); COUNTER.value(Value); test TST("TST"); TST.clock(CLK); TST.go(Go); sc_trace_file *tf = sc_create_vcd_trace_file("wave"); sc_trace(tf, COUNTER.connect1, "jk1"); sc_trace(tf, COUNTER.connect2, "jk2"); sc_trace(tf, COUNTER.connect3, "jk3"); sc_trace(tf, COUNTER.connect4, "jk4"); sc_trace(tf, COUNTER.connect5, "jk5"); sc_trace(tf, COUNTER.connect6, "jk6"); sc_trace(tf, COUNTER.connect7, "jk7"); sc_trace(tf, COUNTER.connect8, "jk8"); sc_trace(tf, CLK, "clock"); sc_trace(tf, Value, "SystemC value"); sc_start(20000, SC_NS); sc_close_vcd_trace_file(tf); return(0); } test is making signal always true jk flip-flop working only falling edge so I'm using clk.neg() counter have 8 flip-flop. first flip-flop clock accept main clock and second flip flop accept first flip-flop's q1 value the other flip-flop connected same way to second flip-flop is there any problem?? I can't find any problem but I can't see anything in GTKwave please tell me why. I need your help (P.S : Actually I can't speaking English very well. so please understand I'm using wrong grammar or vocabulary. Thanks)
  • Create New...