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  1. Hello All, I want to understand usage of noexcept with SystemC. I read that using noexcept will provide me performance benefits! My doubt is how shall I label a member function noexcept, if it is using a SystemC or a library which throws. Following piece of code is self explanatory and needs assistance on correct usage of noexcept. # ifndef MYNOEXCEPTSCCLASS_H_ # define MYNOEXCEPTSCCLASS_H_ # include <systemc> # include <aLibraryThatThrows> template < typename Tinp , typename Tout > class myNoExceptSCClass : public sc_core::
  2. Hi, I have 2 modules: one Test Bench (TB) and a Device under Test (DUT). The TB has an output port (p_out) to simulate a power on (bool). The DUT has an input multiport (p_in) and inside the DUT there are many modules M with one input port (x_in) connected to (p_in). The idea is to simulate a power on througn TB that is distributed to all internal modules of DUT. Here are the declarations: in TB : sc_out<bool> p_out; In internal moules of DUT: sc_in<bool> x_in; In DUT: sc_port< sc_signal_in_if<bool> , 10, SC_ZERO_OR_MORE_BOUND> p_in; E
  3. I am new to systemc in ubuntu 14.04 and I am trying to setup up eclipse for a systemc small project. I followed the the provided README in systemc-2.3.1 and the INSTALL to install the library. I then used tutorial here to set up eclipse. The problem is that I have a syntax error tell me that sc_signal_resolved could not be resolved. below is a sample of my code: #include <systemc.h> int sc_main(int argc, char ** argv) { sc_signal_resolved zero, one; // in the rest of the code I will use the zero and one passing them to some gates. return(0); } Please how do I solve this. In Wi
  4. Hi all. I'm testing some codes to better understanding tlm. In this moment I have a block with this variable : std::map <tlm::tlm_generic_payload*, unsigned int> queue; Basically a place when I store my transactions using trans pointer as key. This variable is accessed by 2 threads. On as input and one as output. Input is fast, output is slow. Threads Input wait until a location (I check my max size) is free and fill it. In system C I used sc_mutex to check lock and check it every X ns (wait(X,SC_NS)). In tlm I don't want to used fixed time but wait unt
  5. I am trying to code a very generic module that takes the number of elements of a sc_vector of sc_in from an argument. This module looks like: transformation_arbiter.h using namespace sc_core; using namespace sc_dt; class transformation_arbiter : public sc_module { public: sc_in<bool> clk; sc_vector< sc_in<bool> > enable_in; . . . private: unsigned pre_rep; public: SC_HAS_PROCESS( transformation_arbiter ); transformation_arbiter( sc_module_name trans_arbiter, unsigned ext_pre_rep ): sc_module( trans_arbiter ), pre_rep( ext_pre_rep
  6. Hi, I have some situations in my models where I have to write a signal from different drivers. To avoid 'multiple drivers to a signal' error I add SC_MANY_WRITERS flag. Is there any way to allow multiple driers to a signal other than putting above flag? I know about sc_resolved but it works only for sc_logic. whenever i regenerate netlist using tool I had to add the flag manually as the tool doesn't have any way to know its a signal with multiple writers.
  7. I didn't find an efficient bug report entrance so I decided to post it here to see whether people think this is a bug or not. I'm trying to use Ralph's solution to reset the sim context (see http://forums.accellera.org/topic/2273-problem-with-re-instatiation-of-modules/). However, that only works well with those modules that don't have a reset signal. I spent some time debugging this with reset signal and found that: This method, sc_reset::reconcile_resets() at src/sysc/kernelsc_reset.cpp:160, is supposed to iterate over all things in reset_finder_q, a static linked list of sc_reset
  8. I am a bit confused about the correct usage of the SC_REPORT_* macros. In "sysc/kernel/sc_simcontext.cpp" we have: SC_REPORT_INFO("/OSCI/SystemC","Simulation stopped by user."); The above is helpful as it produces easily parseable output. Whereas in "sysc/kernel/sc_object_manager.cpp" we have: std::string message = result_orig_string; message += ". Latter declaration will be renamed to "; message += result_string; SC_REPORT_WARNING( SC_ID_INSTANCE_EXISTS_, message.c_str()); This is not so helpful, since it is not clear where the error comes from when analysing output. A quick grep
  9. I'm trying to run uvm-systemc on macosx. Link to download: http://accellera.org/images/downloads/drafts-review/uvm-systemc-1.0-alpha1.tar.gz In the install flow, ../configure works fine, but on make i get this error: Making all in macros CCLD libmacros.laar: no archive members specifiedusage: ar -d [-TLsv] archive file ... ar -m [-TLsv] archive file ... ar -m [-abiTLsv] position archive file ... ar -p [-TLsv] archive [file ...] ar -q [-cTLsv] archive file ... ar -r [-cuTLsv] archive file ... ar -r [-abciuTLsv] position archive file ... ar -t [-TLsv] archive [file ...
  10. I am writing I2C model (as per my requirement) which include master.cpp and slave.cpp. There are 2 signals: SDA and SCL, both are type of sc_inout_resolved in both the files. Connection and Port binding is done perfectly in test bench as well. I am controlling SDA & SCL in file called master.cpp. While transferring ack from slave to master, SDA will be controlled by slave.cpp (writes SDA 0). After this again master.cpp should control the SDA line for further transactions. But once controlling on SDA switches to slave.cpp, unable to control SDA again from master.cpp. Writing values(0,1) o
  11. I am writing I2C model (as per my requirement) which include master.cpp and slave.cpp. There are 2 signals: SDA and SCL, both are type of sc_inout_resolved in both the files. Connection and Port binding is done perfectly in test bench as well. I am controlling SDA & SCL in file called master.cpp. While transferring ack from slave to master, SDA will be controlled by slave.cpp (writes SDA 0). After this again master.cpp should control the SDA line for further transactions. But once controlling on SDA switches to slave.cpp, unable to control SDA again from master.cpp. Writing values(0,1) o
  12. Hello all, I am finding that SystemC 2.2 cannot harmoniously compile with boost 1.58 when -DSC_INCLUDE_DYNAMIC_PROCESSES is defined. It creates a condition where SystemC's embedded boost declarations are previously defined in the real boost. Is there any workaround for this without completely hacking SystemC's boost sources to properly embed boost in "sc_boost" namespace instead of it colliding with the boost namespace from a different release? Details of an example error: In file included from /tmp/systemc/include/sysc/kernel/sc_boost.h:58:0, from /tmp/systemc/inc
  13. Good day, I have a question regarding how to determine the appropriate delay value for the wait( ) function call. In the target b_transport callback, we can add delay to the simulation time by passing delay amount to the wait( ) function. In simulation that uses quantum and temporal decoupling that targets super fast instruction accurate simulation, the timing does not have to be very detail (loosely timed). With or without delay in the target callback function will not cause any functional inaccuracy and still we could produce the platform that can support firmware/software developmen
  14. Hi, I have just learned SystemC for a few days. I wonder what's the main function of wait(SC_ZERO_TIME). It means process will wait until the end of this time or wait for a cycle. But, when should I use wait(SC_ZERO_TIME) and what's the sequence if there's two wait(SC_ZERO_TIME) in two thread? Thank you all.
  15. Good Day All, I am a complete noob in SystemC. I am however, working on a simulator which utilizes a few concepts from SystemC. Kernel is picking up on either the Sc_Method or the Sc_Thread. I am aware of the wait command. It can only be used in the sc_thread. But in my code, (excerpt) I am currently using SC_thread and sc_method simultaneously. I wanted to introduce a delay in simulation time in the sc_thread (using the wait command). Is there a way to forward the simulation time in SC_METHOD that is analogous to wait() in SC_Thread. I did change one of the functions to SC_Thread, and
  16. I want to learn how to install systemc-2.3.1 or systemc-2.3.0 on ubuntu 13.04 precisely and step by step. can you help me?
  17. Hi, I have two files. In header file I have two modules `camkii` and `camkii_ring`. The `camkii_ring` contains N number of `camkii` submodule. I thought of using std::vector to instantiate the submodules. See the code below. #ifndef CAMKII_H #define CAMKII_H #include <systemc.h> #include <vector> using namespace std; SC_MODULE(camkii) { sc_in_clk clock; sc_in<double> ca_conc_in; sc_signal<double> v1, v2, v3; void init() { cout << "[Ca] " << ca_conc_in << endl; //cout << sc_get_time_reso
  18. Hi, I'm newbie to SystemC TLM, coming from SystemVerilog UVM world. I would like to model our RTL in SystemC using TLM2.0 to speed up our Software Development process. Our RTL is not memory mapped bus architecture and we would like to use custom transaction class instead of generic payload. Is it possible to do that using TLM2.0? If yes, could you please provide me with an example. Also, I have four TLM ports communicating with each other in the same model. How does one b_transport method works with all four ports? Is it a good idea to make a model in SystemC rather than having
  19. Hi, Does SystemC support queue like SystemVerilog? I want to create dynamic array in SystemC TLM2.0, can any one suggest a better way to do it? Thanks Zubin
  20. Hello, I am having an SC_THREAD as follows // // SC_THREAD(my_proc); sensitive << event_1; dont_initialize(); // // // void my_proc() { while(1) { wait(10,SC_NS); cout << " Display ok"; wait(event_1); } } My question is i am having an situation where this event get triggered repetedly in short instance of time, lets say at time t=2 ns it get triggered then SC_THREAD starts, then again it get triggered at t=4ns, but this triggerring of event goes unnoticed. I saw some post and from them i got to know that i cant even use sc_event
  21. Hi all, After developing a virtual platform using SystemC with TLM, and also several peripherals (IP) model in high-level (LT), I realised that if in RTL design there is a UVM to say that the design is "okay". How about in high-level? Is there any methodology that we could adopt? If there is none, may I ask for your suggestion on how to verify our own SystemC TLM (LT) design? The SystemC Verification subforum seems to be obsolete, so I posted it here. Really appreciate any kind of advice and solution. Thank you. Regards, Arya.
  22. Hi Guys, It is my first day to read SystemC tutorial, forgive me if the questions are silly. I debugged following code in Visual Studio 2008 (64 bit) by setting break point at the start of do_test1 and do_test2, to my suprise, the code is running in the same thread of the sc_main function. I didn't debug in Linux environment. However, by searching the source code, I found the "pthread.h" was included by some SystemC library source code. Question 1: In Windows, will the SC_THREAD create a real thread? Or it is always in the same thread of sc_main? If this is the case, m
  23. What is SystemC ? Roughly I think it's a language or more specifically a library useful to create software representation (not synthesizable) of an hardware at an abstarction level higher than RTL (- which is synthesizable). Please correct me if I am wrong, Also help me with some standardize definition. What is architectural exploration ? And How SystemC and TLM is useful for it ? If someone working in a systemC domain, could they classify themselves as a software engineer ? Where does it classify ? Which is more appropriate semiconductor industory , EDA or ESL domain ? How someon
  24. I start to learn SystemC and SCV. But I don't have much experience on complex Makefile as the one provided in the install package by SCV. It is too hard for me to understand who the files are really compiled. I am not sure if any one can provide simple Makefile template (Only Linux platform is OK). Thanks.
  25. Hi all, First I apologize if I am using the wrong forum for the question. Please, I would like to know whether someone here could give updates on uvm-sc status. When will a first public release be available ? Regards
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