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  1. Hi, I am currently trying to load modules from external dlls into a systemc application. Basic info: compiler gcc (from cygwin) x64 bit os: windows 7 Also I am using Systemc-AMS but as this appears to be a "problem" with the systemc core I posted it in this forum (feel free to move if inappropriate). The modules are build as shared libs and can can be loaded without problems (using the LoadLibrary function). While I can connect the ports with signals the runtime complains about "no driver" during simulation. As the same code compiled directly into the application works I assume
  2. Hello, I have a Packet class, that for the last week I had to overload some operators ot make it compile using SystemC. Currently I'm trying to instantiate this class in the main file to start testing and I am having compilation issues. The custom class: from my_defines.h typedef sc_bv< _DATA_SIZE > particle_t; #include <systemc.h> #include "my_defines.h" class Packet { public: sc_bv< _BITADDR > _field1; sc_bv< _BITADDR > _field2; sc_bv< _INDEX > _index; particle_t _data; virtual ~Packet(); Packet()
  3. Hi guys , I'm representing a systemC TLM platform in IP-XACT, I finished with systemC modules. Now, each systemC module representing a functional hardware block has to be attached to a c++ object in order to represent some non functional information. Please, is it possible to represent this information within IP-XACT ?? Thanks
  4. Hi All , I am new to SytemC and I am designing a FIFO . When I run the make file I am getting an error " no match for ‘operator=’ in ‘((sync_fifo*)this)->sync_fifo::wptr = 0’ " . I guess this has do with the sensitivity list of wptr and rptr but I am not sure how to fix it.I have highlighted the lines where I am getting error . It will be really helpful if someone could explain this . Thank you #include <systemc.h> SC_MODULE (sync_fifo){ sc_in_clk clk; sc_in<bool> rst; sc_in<bool> rd_wr; sc_out<bool> full; sc_out<bool> empty; sc_in < sc_uint&l
  5. Hi everyone, Recently, I am studying systemc and have a problem on semaphore channel. Actually, I found an example of semaphore channel on asic world (http://www.asic-world.com/systemc/channels3.html). This example provides 3 processes (SC_CTHREAD): bus_semaphore(), do_read() and do_write(). like below, ------------------------------------------------------------------------------------------------------- #include <systemc.h> SC_MODULE (sc_semaphore_example) { sc_in<bool> clock; sc_semaphore bus; int cnt; void bus_semaphore() { while (true) { wait(); cout << "@" <
  6. Hello everybody, I would like to know if AMS and SystemC have two different schedulers. If yes then how do they interact? Moreover i would like to ask how many extensions does SystemC has? Thanks in advance
  7. Hi Experts, How do I pass "Maps" within constructors while using a SystemC struct? I want to instantiate this module 4 times and use 4 different maps for each instance. struct Detector: sc_module { SC_CTOR(Detector) { for (int i = 0 ; i<10 ; i++) { in_map= map[0]; // in_map has been declared as private & map is passed on through the constructor } } Thankyou in advance!
  8. Hello all, I'm simulating MOESI protocol for L1 caches in SystemC. I'm getting different results for the same source code when running in SystemC 2.3.0 and SystemC 2.3.1 versions in different machines. Could anyone kindly pass some light on this topic? Machine1: Linux 3.13, Ubuntu 14.04, SystemC 2.3.1, Intel Pentium Dual Core processor. Output - Machine 1: CPU Reads RHit RMiss Writes WHit WMiss Hitrate 0 6 0 6 4 0 4 0.000000 1 34 0 34 22 0 22 0.000000 2 35 0 35 43 0 43 0.000000 3 39 2 37
  9. Hello Accellera Forum, I'm trying to execute the IP-XACT example of the Leon2 on the accellera page. I'm using systemc2.3.1 on windows8 with cygwin gcc 4.8.3. I try to run the makefile in the directory TLM2, but I´m getting following error: Makefile:130: recipe for target '../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/tlmreg_Leon2_uart.o' failed make: [../../spiritconsortium.org/Leon2TLM/uart_tac/1.0/tlmsrc/src/tlmreg_Leon2_uart.o] Error 127 (ignored) g -m32 -O3 -fpermissive -DVERBOSE_GLOBAL -Wno-deprecated -DSC_INCLUDE_DYNAMIC_PROCESSES -I/cygdrive/c/systemc-2.3.1/
  10. Hi Experts, 1.I have seen that Offsets of a Slave Module is described in the Memory Maps in Component Description. Is it possible to describe Offsets in the top design? The motive is to repeat various instances of a Slave Component in a design, each slave instance having a different Offset. 2. Also, I have a SystemC architecture in which I instantiate the same bus several times. But I connect each bus instance with a different number of modules. This is because the bus possesses MultiPassthrough Sockets. How can I reproduce it in IP-XACT? Should I have a custom Component for each
  11. I have used Modelsim to compare simulation results between a C model encapsulated in SystemC to its VHDL implementation, mostly with a GUI, for hardware verification. I am trying to see how SystemC can be used for Software validation and/or regression testing using a SystemC testbench that has software modules, SystemC models, and VHDL HW modules when fidelity is needed. I am assuming the open-source SystemC simulator does not support VHDL natively so a VHDL simulator would be needed like modelsim. What is the best way to use the SystemC open source simulation to make calls to a VHDL si
  12. I have a question which probably is quite stupid. I developed a Software in the Loop framework in SytemC. This framework is supposed to call in specific discrete time instants some modules to execute. For instance suppose we have module A and B. Module A has to be executed every 10 ms and Module B every 20 ms. The execution order has to be first A and then B when both modules have to be executed. I am able to do that by having a coordinator module triggered by a clock of 10 ms. Every module ( module A, B and scheduler) are related with an event. Module A and B they look like this: while
  13. Hello, I have a SystemC program encapsulated into a C++ class allowing to interact with a SystemC model. In order to easily call that program from a scripting language, I would like to generate a shared-library containing all my SystemC program and the SystemC library. Is it different from generating a classical C/C++ shared-library? How can you deal with the sc_main required by the SystemC? Can you point me to some documentation about that topic, I didn't find anything about it for SystemC on the internet... Thank you! Regards! J-B
  14. Hello, I am using systemC-2.3.1 which I think has started supporting native windows(x64) build. I have build the library of systemC using the msvc solution file in visual C++ express 2010. The library is generated under x64/Release directory and I didn't get any build error. But while linking this library with my application it throws an error message as follow: systemc.lib<sc_time.obj> : fatal error LNK1112: module machine type 'x64' conflicts with target machine type 'x86'. I am compiling my application with visual studio command prompt. Am I missing here something
  15. Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog
  16. I am trying to use an sc_vector of modules with a custom creator to pass constructor arguments. It seems to work and run through the entire program, but at exit causes a segfault. GDB shows that this is due to to sc_vector calling the destructor of the module. I have no dynamically-allocated memory or pointers in the module. Here's the overview: outside of sc_main (global -- but I also tried inside of sc_main): -------------------------- struct create_mod { unsigned int m_arg1; unsigned int m_arg2; create_mod(unsigned int arg1, unsigned int arg2) : m_arg1(arg1), m_
  17. Good day. I am new to SystemC and TLM. Here I am implementing producer-consumer model with a bus and memory model. The synchronization between producer-consumer is done using semaphore. I add DMI feature to the simulation. So the idea is to give producer direct access to the memory region. The same goes for the consumer. What I expect from doing this is to gain faster simulation time. However, at some point of my experiment it shows that using DMI takes longer simulation time. Is this normal to happen? Or I might implement the DMI in the wrong way? Thank you. Best regards,
  18. I need to develop a SystemC model for a new (nonexisting) bus architecture, change it whenever needed and investigate its performance with every change. I do not know how to start on that, there is no tutorials or books that focus on using systemC in practical projects, all that's available is on the language itself. how do I approach this problem? how to start?
  19. Hi All: Get to implement a timer module in SytemC-TLM. And it is at LT level. The Time used for interrupt generation is from sc_time_stamp. My current implementation is using TLM payload event queue, which means the timer caculates the expected wait time for the request and do "notify(x ns)" for the payload event queue. Which the drawback is: 1.When I add the cancel function for a ongoing time request, I can't delete the "time request" from the event queue. I do a workaround like saving some tags when the timeout happened to achieve the "cancel" 2.When I add a stop function
  20. Hi everybody, I have a simple question (not so sure if the answer is simple too). Is it possible to "pause"/"halt" the simulation temporarily? It would be useful for me in two scenarios: Whenever the simulation reaches a specified point in the code. Just like a breakpoint, but not having the need to use a debugger. So whenever the user presses a key, the simulation goes on. Whenever the simulation reaches a point, where a user needs to send an input. It is similar to the previous one, but the here the user would need to enter an input (int, double, string, etc.). I understand that thi
  21. I have a platform for native simulation, composed with sc_main.cpp, native_wrapper.cpp, native_wrapper.h, hardware.... I have to implement another CPU but I didn't find a method to make this. Because extern "C" is needed since the software is compiled in C and is linked against native_wrapper.cpp, which is compiled in C++, for this, we call methods of soft in a this manner, using “NativeWrapper::get_instance()->method_name()” below you can see code of sc_main.cpp, native_wrapper.cpp and native_wrapper.h.Thanks for your help code for native_wrapper.h #include "ensitlm.h" #include "native_
  22. Hi again! Maybe this is too obvious, but I've been wonderin for a while now and never found the answer (and dared to ask for it ). Is it possible to directly pass whatever comes from an tdf_in port to a tdf_out port? Not only that, is it possible to do it in a sc_module instead of a sca_module? For a better explanation I'll leave a piece of code. Let's say I have: #include <systemc-ams> class some_module : public sc_core::sc_module { public: sca_tdf::sca_in<int> in; sca_tdf::sca_out<int> out; some_module(sc_core::sc_module_name nm); }
  23. Hi, I am getting errors like below: Trace ERROR: No traces can be added once simulation has started. To add traces, create a new vcd trace file. Code of memory.cpp corresponding to error: Memory::Memory(sc_core::sc_module_name name, unsigned int size) : sc_module(name), m_size(size) { tf = sc_core::sc_create_vcd_trace_file("trace_data1"); // tracing, trace file creation tf->set_time_unit(10, sc_core::SC_US); storage = new ensitlm::data_t[size/sizeof(ensitlm::data_t)]; } // Destructor Memory::~Memory() { // close trace file sc_close_vcd_trace_file(tf); delete []
  24. Hi Can anybody please tell me how to write a transactor for an existing System C model? I can write a systemC model as well as a LT TLM model. But i don't know how to interconnect both of them using ports. Any valuable help would be appreciated. Thanks
  25. We are using TLM to pass transactions from SystemVerilog to SystemC. I have two cases where I am stuck. Actually, it is the same case, but I have two angles to my question. 1) Is it possible to still use a TLM setup, but without a transaction type. (I realize that this is contradictory to the acronym.) A c-model has a debug function which takes no input arguments. So, when the SV testbench runs into a problem, it can call this function in the SystemC/c-model. As all of our connections now are sc_port/sc_export, with TLM, I'd like to stick with that flow if possible, rather than addin
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