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  1. void Wcache0::getAddrForSingleWeight(const channel_t co, kernel_t kernel_1, const weightaddr_t ci_offset, PEID_t &PEID, blockID_t &blockID, rowID_t &rowID, weightID_t &weightID) Hi, Can we pass arguments inside the process in SystemC. If Yes then how we have to register the process in the constructor? Thanks . Below is the MODULE Wcache0 and I am trying to write getAddrForSingleWeight process which will be called inside another pr
  2. Hi I have written a sample code in SystemC. I am defining some typedefs and global variable outside SC_MODULE. Is that fine? and plus I am also defining the member function as static. Please correct my code. Thanks
  3. Saw the UVM-SystemC-1.0-beta1 download link, try to install it, but according to the INSTALL file, I can't find "configure" in the package. How could I install it?
  4. Hi all, i'm implementing a timer/counter(8-bit) that should not increment on every clock and i'm not supposed to provide any input clock port . But i need clock period in my design so my question is " How would i provide clock period(through constructor)?" here is the link to my working code on EDAplayground : http://www.edaplayground.com/x/4_dY if there is any problem in my code please feel free to tell me. regards, jatin
  5. Hi all, is there any way to implement the intra assignment delay in systemC without using sc_event()? for example : in verilog we write out = #10 in1 + in2; // intra assignment delay. how would i implement the same in systemC? regards, jatin
  6. Hello, I am using SystemC 2.3.0. I am wondering how I can profile the SystemC library. I found we can use options like "--enable-debug" and "--disable-optimize" for debugging and optimization, respectively, but I was unable to find such an option to enable profiling. I need to use gprof and pass "-pg" options when building SystemC. Any help is greatly appreciated! Thank you in advance.
  7. I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals?
  8. Hey, Kahn Process Networks are defined by the usage of unbounded FIFOs with blocking reads and non-blocking writes. I read on several sources that KPN with bounded FIFO size (i.e. blocking read and blocking write) can be implemented with SystemC (e.g. Grötker et al). It seams that the event based scheduler in SystemC behaves different like data-driven scheduler or a demand-driven for KPNs. I simulated the networks of Park's Dissertation shown on page 36 and 42 which should end up in an artificial deadlock (deadlock which occurs because of blocking write). A global artificial
  9. Hi, I am getting the same sequence of random numbers every time I run my SystemC code ... there is too much code to post here, so I will attempt to describe what I am doing ... I have written a DUT (SC_MODULE) with 9 input ports and I have written a Driver (SC_MODULE) to drive one of those ports, I have instantiated 9 Drivers and 1 DUT in sc_main ... the Driver uses rand() ... Each Driver produces the exact same sequence of random numbers ... I didn't some looking on the C++ forums and tried the following ... 1. Adding srand(time(NULL)) to the Driver ... but it won't c
  10. I am a novice at SystemC (some OOP background but not much) ... I am getting an error for the code below ... ../src/xor2.h:20:31: error: invalid initializer for array member 'nand<2> xor2::nand2 [4]' I have much more complicated but netted my problem down to this much simpler and smaller example ... #include "systemc.h" template <int width> SC_MODULE(nand) { sc_in<bool> A[width]; sc_out<bool> F; void nand_func() { F.write(!and_reduce(A)); } SC_CTOR(nand) { SC_METHOD(nand_func); sensi
  11. Hello There is an existing model with tlm1.0 sockets - sc_port and sc_export. Is it possible to bind these sockets to tlm2.0 initiator and target sockets? If yes, then what is the conversion procedure involved? I'm new to SystemC, any help/insight on this is appreciated. Thanks.
  12. Hello, Is there a way to generate execution trace for a SystemC project? Thanks, R.Adiga
  13. Hi everyone, my initiator is writing to a specific register but I want to block the initiator if a certain bit of the target register is set (1). is there a way to do that?
  14. Hello All, I am working on SystemC-UVM based testbench. I have created UVM based testbench using UVM code generator. Here I am using three different agents in UVM generator which I have defined as a part of the configuration file which was further being provided to UVM code generator to generate test bench skeleton. And here, in of the agent driver, the code snippet is as: // Drive the inputs of the DUT UVM_INFO(this->name(),"Driving transaction:",0); req.print(); // TODO put your code here But when I try to read the value in my test-cas
  15. Hello, I'm just starting off with TLM-2.0 and would like to explore more about the use cases for byte_enable_ptr. In TLM manual, I see that " A value of 0 shall indicate that that corresponding byte is disabled, and a value of 0xff shall indicate that the corresponding byte is enabled"; Does this mean that we can switch between 0xff and 0x0 if required for every transaction? TLM manual also states that Byte Enable can be used to create burst transfers, can anyone please explain this? Thanks, R.Adiga
  16. Folks, I have requirement to calculate bandwidth per socket. This means I need to count how many transactions were sent on a given socket, and also pass clock information. Are there any example of customizing socket where I can calculate these things and print of at the end of the simulations.
  17. Hi all, im a a student and my project is about systemC, im searching for a freelancer who can help please send to me a private message. thank you
  18. hi all, i want to integrate systemC and openCv in visual studio 2015 to process images for motion detector system. it is possible to do that ? thanks
  19. SOLVED: Nevermind, I made some mistakes in calling the wrong methods for writing/reading from ports. Thanks for your attention anyway! I'm trying to implement this example of a memory and a cpu that are communicating. CPU <==> MEM The modules use a single bidirectional data-line for reading/writing. I defined a signal in sc_main: sc_signal<int,SC_MANY_WRITERS> s_memdata; which I connect to the CPU and MEM module through their ports: sc_inout<int> p_memdata; The CPU is writing to the s_memdata signal: p_memdata.write(getrnddata());
  20. In my project there are several functions which perform SystemC simulations (each has its own declaration prelude and sc_start()). So they are constructed as follows: // first Simulation: sc_signal<double> s1_sim1; .. ControlFoo<double> *cf = new ControlFoo<double>(); cf->Foo_port(s1_sim1); .. sc_start(); // works fine delete(cf); .. // second Simulation: sc_signal<double> s1_sim2; // this leads to an exception The first simulation runs as desired until the sc_stop(). But when I try to declare new sc_signals after the first simulation is completed then it come
  21. Hi, i am trying to declare an sc_port from which i want to send a struct (ressource) between two different modules. I declared an interface and a channel to implements the send and receive interface methods but i am experiencing two errors. The first one is C2011 'class ' type redefinition, the second one is C2504 base class undefined. Now the Interface is very simple: //comm_interface.h class comm_send_interface : virtual public sc_interface { public: virtual bool send(ressource) = 0; // send a ressource virtual void reset() = 0; // empty ressource list };
  22. I created vector of fifos: sc_vector<sc_fifo> fifos; and in my constructor: template <unsigned S> class my_chnl : public my_chnl_if, public sc_channel { sc_vector<sc_fifo> fifos; //vectors of fifos //----------------------------------------------------------- public: //----------------------------------------------------------- //constructor //----------------------------------------------------------- explicit my_chnl(sc_module_name nm, unsigned _size = 4) : sc_channel(nm), fifos("FIFO") { fifos.init(S, _size); } .....
  23. Hi there, I'm an engineering student from Venezuela and working on systemC for a class project. I'm having a bad time trying to make a tri-state buffer model on system C. I know there is sc_logic and sc_lv but I just don't know how to work with this two data types. I'm working a project (a microprocessor) and I need to model a tri-state module to hook up with my registers so I'll be able to have control on the data coming out of the registers. In case you wonder here is more info https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Build/implRegFile.html Any idea on how
  24. I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!
  25. I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!
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