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  1. In the SystemC 2.3.2 review thread Ameya Vikram Singh (@AmeyaVS) reported the following observation: I'll open a separate topic to discuss the details.
  2. Hey everyone, As of now , i am reffering textbook "SYSTEM C-FROM THE GROUND UP". I wanted to have the solutions of example problems given in that book. Can anyone,please tell me where can i find them? I am not able to find solutions on the link provided in the textbook. Thanx in advance. Regards, Veeresh K
  3. In my code the variable 'inter' is changing its value by itself whenever, it is read/assigned. Please help void dff(){ cout<<"IN DFF"<<endl; cout<<sc_time_stamp()<<endl; wait(10,SC_NS); cout<<sc_time_stamp()<<endl; while(true){ wait(); cout<<"\nIN = "<<in.read()<<" TIME" <<sc_time_stamp()<<endl; inter.write(in.read()); cout<<"\nInter before wait= "<<inter.read()<<endl; wait(10,SC_NS); out.write(inter.read()); cout<<"\nInter
  4. Hi , I am trying to trace out the wave for the input and the output. I have tried for different ways,but not getting the desired results. One of the way was,i created 2 same signals with diff. name in testbench file and tried to trace ,but i was not successful in doing so. Any suggestions to do? Thank you. ? Ps:- I have attached the code through which m trying to trace.Plz,help me out with this.I have modified the code according to the errors,So thats the reason for using namespace sc::core while declaring fifo tracing input.I am posting full code along with the
  5. Hey everyone, I am trying to trace out the wave for the input and the output. I have tried for different ways,but not getting the desired results. One of the way was,i created 2 same signals with diff. name in testbench file and tried to trace ,but i was not successful in doing so. Any suggestions to do? Thank you. ? Ps:- I have attached the code through which m trying to trace.Plz,help me out with this.I have modified the code according to the errors,So thats the reason for using namespace sc::core while declaring fifo tracing input. /////////
  6. Hi. I have taken this example from a book and tried to execute it,But i got few errors. I have compared this code with std 2011 and made changes according to that like using namspace sc_core . I am not able to find a right solution for this one. Can someone plese help me out with this.I have posted the code below along with the error,check it out. Thank you. //error////////// In file included from testbench.cpp:6:0:head1.h: In member function 'void www::woperation()':head1.h:16:9: error: 'class sc_core::sc_port<sc_core::sc_fifo_out_if<int&
  7. Hi, I am new to system c. I am trying to learn it step by step,but getting messed up with arrival of every new topic. Any suggestions for good book ? Currently i am studying system c primer by J.Bhasker. Please, help me out. Thank you.
  8. Hi, It seems I have hit a bug in VCD tracing implementation in SystemC release 2.3.2. Here is the bracktrace captured in GDB: (minimal example available here: https://github.com/AmeyaVS/SystemC_ramblings/tree/dev) as one can observe the exception: SIGFPE in systemc-2.3.2/src/sysc/tracing/sc_trace_file_base.cpp:268 due to divide by zero error. GNU gdb (Ubuntu 8.1-0ubuntu3) 8.1.0.20180409-git Copyright (C) 2018 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and red
  9. Hi, I am new to SystemC, I have installed SystemC 2.3.2 successfully in Visual Studio 2017. The only problem that I have is with sc_main() function. The compiler complained the entry point cannot be found. I understand that the default entry point in VS is int main(). I have read IEEE Std 1666-2011 clause 4.3 about sc_main() and sc_elab_and_sim(). I tried to use following code to start simulation. But it failed. The compiler showed error message: "identifier "sc_eabl_and_sim" is undefined". int main(int arg, char* argv[]) { sc_elab_and_sim(arg, argv); //The rest code for simulation
  10. Hi, I'm trying to use a SC_METHOD in my simulation. Here is the code: gcrypt::gcrypt(sc_module_name name): gcrypt_base(name) { SC_METHOD(on_clock_update); sensitive << clock; dont_initialize(); }; void gcrypt::on_clock_update() { if (clock.read() == 0) { SC_REPORT_WARNING(name(), "Invalid clock port value of 0"); _ns_per_cycle = 0; return; } _ns_per_cycle = 1e9 / clock.read(); } The gcrypt_base constructor is: gcrypt_base::gcrypt_base(sc_module_name name) : sc_module(name), ... { ... } I get this exception thrown by SC_METHOD: Except
  11. Hi, I am new to SystemC. I have two questions. 1) Do sc_thread generates separate Linux thread for each call and what is the difference between the POSIX thread and sc_thread? 2) Why systemC has no parallelization scheme? The SystemC scheduler uses cooperative multitasking and cannot exploit fully the potential of SMP workstation.
  12. Hi I have to use the sc_vector command to pass an array let's say Array[16][16] between the modules. Kindly can you tell me how to write the input side vector at the MODULE A and output side vector at the MODULE B to pass this array. I am beginner and donot know how to use the sc_vector command. Thanks
  13. Hi, I want to run the diagram given below. I am executing the modules with the respective processes but it only execute once and then the loop dies. I am providing the static sensitivity to the processes inside the modules e.g. sensitive<< sig1; and so on. How to make the execution multiple times as mentioned in the STEPS in the Diagram. I need help in running the STEPS multiple times before we proceed to the next step in System C code. Thanks
  14. Hi I am running the Sequence of Modules in the flow like: 1) Memory Module 2) Data fetching to the Weight and Image_Cache Modules 3) Processing_PIXEL_MODULE and so on. But I wanted to go back from Processing_pixel_Module to the Image_Cache Module for Cache refill. Can You help me that how can I achieve this. I wanted to go back to the Image_Cache Module to refill the Cache from the Memory module. thanks.
  15. Hi The TLM_READ_COMMAND IS NOT READING THE DATA ARRAY COMPLETELY. What can be the possible reason. I have allocated an array through malloc command in the memory module. and Then from the second module i am trying to read that array using the TLM_READ_COMMAND but the array is not being read completely and it stops in the mid somewhere. Just not running any further without showing any error. What can be possible reason for this . Thanks
  16. Hi I have to load a floating point data from the binary file and save it in an array inside the MODULE_1 (Memory) and then I wanted to transfer the content of that array from MODULE_1 to Another MODULE_2 (CACHE) through TLM. Can You guide me how to save an array in MODULE_1 (Memory) and transfer the floating point data to another MODULE_2 (Cache) through TLM. I am trying to read the data from CACHE to MEMORY but TLM_GENERIC_PAYLOAD does not access the correct memory address of the array elements to read from and therefore I am just reading some garbage value. A help through sample code
  17. // MODULE 1 WRITING THE OUT1 to Value 1 SC_MODULE(MODULE_1){ public: //-------------PORTS DECLARATIONS--------------------------- sc_in<bool> reset; sc_out<bool> out1 ; // ---event sc_event sig_written; public: void Process(); public: SC_CTOR(MODULE_1){ SC_METHOD(Process); sensitive << reset; } void Process() { if (reset == 1) out1.write(1); sig_written.notify(); // to make it runnable within the execution phase
  18. Hi I have 3 to 4 modules and they have 3 to 4 inputs but to synchronize the timing of inputs as they all have to have specific value only then my THREAD PROCESS should run, I am using value_changed_event inside the THREAD PROCESS of the MODULE by using wait(sig.value_changed_event()). But In some MODULES, I am initializing large arrays and due to this when the value changes then it rerun from the 1st Module to the Last and stops in the mid-way displaying the stack over flow as the exception. What Should be the possible solution for this ? I have Increase the Stack size upto 1Giga but st
  19. Hi In TLM, I am connecting two modules with the Initiator socket and target socket. My question is that "Is that possible to have also signal based connection between the modules as well as the Socket based connection " ? Can we have communication in both ways in SystemC ? Thanks
  20. Hi, I have to Allocate Memory for my data in SystemC. We Use malloc in C Language and New in C++ to dynamically Allocate Memory. But today I have read that we cannot use New and Delete Operators in System C as they are not synthesizeable. Which command should I use for Memory Allocation in System C. Thanks.
  21. Hi, We use SystemC to define specific Hardware Blocks like Memory, Caches and Bus etc. We define Header and CPP files and Include processes to define the functionalities being done by each module. BUT let's say Now we have to define the general settings of the Whole Network (like NEURAL NETWORKS AND DEEP LEARNING NETWORKS) which include Two or three STRUCTS about configuration and we make additional Header and CPP file for this. WILL THAT BE CONSIDER AS A FURTHER HARDWARE IN THE SYSTEM C Design. Is that allowed or not ? This is a general question? Please explain me this in detail? Thanks
  22. hi, I want to implement systemC TLM design that uses a simple bus to communicate between the two separate modules. I want to know how to use systemc built in simple bus. Please help me in this regard. Thanks in advance.
  23. hi, I want to implement systemC TLM design that uses a simple bus to communicate between the two separate modules. I want to know how to use systemc built in simple bus library. Please help me in this regard. Thanks in advance.
  24. Hi. I am working on the Design Flow of the Given Architecture and I making the SystemC Model on the basis of the given diagram description. I not included in my System C Model the shared DRAM. Can You guide me How I have to model the Shared DRAM near Memory Controller Box in System C (As a Module or not ?) as shown in the first picture. Give me some System C Block diagram for this architecture as I am new to the System C. Thanks
  25. Hi, Can we pass arguments inside the process in SystemC. If Yes then how we have to register the process in the constructor? Thanks . Below is the MODULE Wcache0 and I am trying to write getAddrForSingleWeight process which will be called inside another process which is register as SC_THREAD. void Wcache0::getAddrForSingleWeight(const channel_t co, kernel_t kernel_1, const weightaddr_t ci_offset, PEID_t &PEID, blockID_t &blockID, rowID_t &rowID,
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