Jump to content


  • Content Count

  • Joined

  • Last visited

  • Days Won


Reputation Activity

  1. Like
    sonalidutta got a reaction from maehne in Dynamic Assertion-Based Verification for SystemC   
    In http://www.cs.rice.edu/CS/Verification/Theses/Archive/dtabakov_dissertation2010.pdf:
    An assertion is an LTL formula with a set of sampling points that describes a formal property of your SystemC model under verification. In Assertion-based Dynamic Verification of SystemC models, each assertion is converted to a C++ monitor class. A C++ monitor class is just a C++ encoding of a deterministic finite automaton. The transition function of the DFA is encoded as a step() function in the monitor class.
    Now the question is when and how frequently to execute the step() function of a monitor class. This is where the sampling points come into the picture. You execute the step() function only when any of the specified set of sampling points occur during your simulation. In the above dissertation, it allows you to sample at different phases of the SystemC kernel, for example: when a new delta cycle begins, when a particular event is notified by the kernel or when a SystemC process suspends. This cannot be done with the unmodified version of the SystemC kernel since all these kernel informations are hidden from the user. So in the above work, the author puts a minimal patch on the SystemC kernel to expose the necessary kernel information.

    But this is not mandatory. You can also only sample at different points in your user model. For that you do not need to modify the SystemC kernel. But allowing sampling also at kernel phases adds to the monitoring power. So as a summary, it is not necessary to change the kernel to do assertion-based verification of SystemC. But since in SystemC (unlike SystemVerilog), the kernel plays a very important role in the simulation, if you change the kernel to expose certain information, it might be useful.
    Universal Verification Methodology (UVM) is a new "de-facto standard" for verification (based on Accellera's marketing materials) (Primer here: http://www.doulos.com/knowhow/sysverilog/uvm/tutorial_0/). UVM is a base class library for hooking up monitors and generating tests, but does not do anything about Kernel events or about generating monitors.
  2. Like
    sonalidutta got a reaction from karandeep963 in School for SystemC, SoC Architecture in India   
    I would suggest you to read the systemC manual A to Z. It is very well-written. It is more like a book than manual. I learned it in that way. Also http://emedia.art.sunysb.edu/debt/downloads/books/System%20Design%20with%20SystemC.pdf is a good book for the initial stage.
  3. Like
    sonalidutta got a reaction from maehne in use of events vs flags   
    SystemC kernel simulates parallel execution of hardware. Processes suspends and resumes. A process can suspend itself and wait for an event to take place. When the event happens, that process resumes its execution. This is the most important power of SystemC. You cannot gain this advantage using flags, even inside the same module.
  • Create New...