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amitk3553

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  1. Like
    amitk3553 reacted to David Black in primitive and hierarchical channel   
    It is worth noting that a hierarchical channel is really just an sc_module that implements an sc_interface. It's purpose is for creating complex abstract channels (e.g. PCIe or AXI). Primitive channels are for smaller (primitive) transfers such as wires (i.e. sc_signal<>).
  2. Like
    amitk3553 reacted to apfitch in primitive and hierarchical channel   
    A channel is simply a class that implements a SystemC interface.
     
    A primitive channel implements an interface and is derived from from sc_prim_channel, and can thus have access to the scheduler (evaluate update).
     
    A hierarchical channel implements an interface and is derived from sc_module, and can thus have all the features of an sc_module (processes, hierarchy etc).
     
    There'd be no point in deriving from sc_prim_channel and then not implementing the update/request-update behaviour.
     
    If you want a channel that is not a primitive channel, and is not a hierarchical channel, you would typically implement an interface but derive from sc_object.
     
     
    regards
    Alan
     
    P.S. To answer your questions more specifically - request_update and update are not pure virtual, so you could ignore them. Though why would you ignore them? If you don't want them, derive from sc_object instead.
    A hierarchical channel is derived from sc_module. sc_module does not have request_update/update, so you can't use them.
  3. Like
    amitk3553 reacted to uwes in Polymorphism in testbench   
    hi,
     
    polymorphism is a general concept. see http://en.wikipedia.org/wiki/Polymorphism_(computer_science). the testbenches we write are essentially software. in that sense all methods to improve creation/speed/maintenance/stability/reuse of software should be in the focus for tb developers too. the concept of polymorphism is one way to improve.
     
    /uwe
  4. Like
    amitk3553 reacted to quanghong in Polymorphism in testbench   
    You can use the polymorphism in UVM as following example:
     
    class driver extends uvm_driver;
    class my_driver extends driver;
     
    module test;
       ....
       driver dr;
       initial begin
           // polymorphism:  wait until run-time to bind the object type
           // You can override either by type or instance.
           factory.set_type_override_by_type(driver::get_type(), my_driver::get_type());
          
           // It is important to use factory before create
           dr = driver::type_id::create("driver", null);
          
           run_test();
       end
    endmodule
     
    Hope it helps.
    Quang
  5. Like
    amitk3553 reacted to dakupoto in role of dynamic processes   
    In perfect agreement with what Phillipp has said, if one is trying to analyze/model hardware,
    absolutely do not use dynamic processes, as there is no such thing as creating hardware
    "on the fly". But if one is examing software, one could use dynamic processes.  
  6. Like
    amitk3553 reacted to Philipp A Hartmann in role of dynamic processes   
    Dynamic processes are especially used in situations when you need to spawn additional parallel execution in your model during the simulation. You cannot use static processes in such cases.
     
    /Philipp
  7. Like
    amitk3553 reacted to David Black in Polymorphism in testbench   
    The simplest examples of polymorphism at work are the UVM factory when you use overrides.
  8. Like
    amitk3553 reacted to Hany Salah in Polymorphism in testbench   
    in case you have such ubus example,,, you have different agents ,, each one is responsible to act like either master or slave ,, It isn't restricted that all agents act in the same way at the same time,, but you have to randomly configure each one to make your test more random and more effective ,, such way ,, you have different agents ,,, each one extended from uvm_agent base class ,, and each one may have the same function name ,, for instance write(),, strope () ,, read() and so on ,, 
     
    Through build phase ,, you called build function through all environments in the same test bench ,, although they have the same name ,, polymorphism play its role 
     
    another example through when run phase ,,, each agent may have his own run routine with the same name run () ,, but they don't act as each other ,, so polymorphism play its role here also 
     
    on Other matter ,, naming function whose main purpose similar like run, is so practical as on complex tests you have high number of agents and scripts and you may get lost in routines' names  
  9. Like
    amitk3553 reacted to David Black in virtual platforms, architectural exploration   
    Virtual platforms can be written much faster than actual hardware implementation and simulate much faster.
     
    Virtual platforms should be written in days vs months. In other words at least an order of magnitude faster to write.
     
    They should execute 100-100,000 times faster as well. This means they can be used before hardware design is completed to develop software on. Also, they can be used in a mixed-level simulation to speed up results of RTL simulations when the focus is on other parts of the system still represented in RTL.
     
    Also virtual platforms can be used to debug problems that are almost impossible to debug in hardware because you can set breakpoints and single step them.
     
    Many other good reasons and uses.
  10. Like
    amitk3553 reacted to dakupoto in How to implement i2c clock synchronization using systemc?   
    Hello Sir/Madam,
    Real world on chip clock synchronization is achieved
    with a bautiful analog scheme - phase locked loop(PLL).
    A phase locked loop can be implemnted in both SystemC
    and SystemC-AMS very easily. An alternative is to use
    derived clocks - master clock triggering several other
    clocks - the derived clock runs at the same frequency
    as the master clock as:
    clkout.write(clkin.read());
    Hope that helps.
  11. Like
    amitk3553 reacted to apfitch in virtual platforms, architectural exploration   
    Google :-)
  12. Like
    amitk3553 reacted to karandeep963 in virtual platforms, architectural exploration   
    Hey CAM,
     
    I have been in conversation with many people around for the same topic. underwritten are some replies:
     
    1: WRT to hardware already built: it can be used as golden reference model for future enhancements as new features can easily be embedded to it then to hardware , thus indeed helping the driver team to run the updated driver on it.
     
    2: in case the SOC already built need to be integrated to some other large SOC then this virtual platform there it is playing the vital role as above
     
    WRT to architectural exploration , needs to create daisy chain equation using matlab or other tool which can thus be simulated using virtual platform: - courtesy : `best architect`
     
    thats all i know , some others may add better.
     
    Regards,
    Karandeep
  13. Like
    amitk3553 reacted to apfitch in transaction concept in UVM   
    You could have a look on TLM Central http://www.dr-embedded.com/tlmcentral/servlet/catalog
     
    It's possible to connect UVM and SystemC together using UVM Connect. That would let you use a SystemC TLM model in an SV UVM environment. Of course you need a simulator that supports both SV and SC to use it.
     
    Alan
  14. Like
    amitk3553 reacted to apfitch in TLM 1.0 and TLM 2.0   
    Sockets are TLM2. Ports and Exports are SystemC.
     
    Alan
    P.S. TLM2 is also SystemC, of course. So perhaps I should say Sockets are features added as part of TLM2.
  15. Like
    amitk3553 reacted to apfitch in TLM 1.0 and TLM 2.0   
    There's a nice summary in section 10.1 of the IEEE 1666-2011 standard,
    Alan
  16. Like
    amitk3553 reacted to apfitch in constraint solver   
    For your first question, try  reading this Wikipedia article on constraint programming:
    https://en.wikipedia.org/wiki/Constraint_programming
     
    The solver is the part of a SystemVerilog simulator that solves the constraints (produces a set of values for random variables that satisfy the constraints).
     
    For your second question, the SystemVerilog standard states "If a solution exists, the constraint solver shall find it. The solver can fail only when the problem is
    over-constrained and there is no combination of random values that satisfy the constraints." Which you could argue means the constraint solver is "powerful".
     
    regards
    Alan
  17. Like
    amitk3553 reacted to dave_59 in Program blocks   
    Modules are used for both design and verification. Modules are instantiated to create hierarchy of other modules, interfaces and programs. Programs cannot contain any hierarchy. Just forget about programs.
  18. Like
    amitk3553 reacted to apfitch in differences b/w ovm and uvm   
    There's a summary on this page:
     
    http://www.doulos.com/knowhow/sysverilog/uvm/
     
    regards
    Alan
  19. Like
    amitk3553 reacted to David Black in Program blocks   
    A module is intended to represent the design under development/test and may be synthesized (subject to appropriate coding guidelines). A program block is intended for verification only. Thus the code in a program is never intended to be synthesized.
     
    If a module were allowed to call a task or function in a program, that would imply that the code could be synthesized. The tools that synthesize would then have to be more complex and consider program blocks. This restriction removes that burden.
     
    Also, program blocks were intended to remove race conditions between verification code and design implementation. If a module could call tasks in a program, then race conditions might occur in as the rules for where things are executed would create problems. [NOTE: This is the strongest reason, but more difficult to follow.]
  20. Like
    amitk3553 reacted to ralph.goergen in Events notifications and wait for events   
    Hi. 
     
    The never ending wait may be caused by race conditions. 
     
    a) Notify with no argument means immediate notification. I.e., all processes sensitive to this event are made runnable in the same delta cycle. This may lead to non-deterministic behavior and should be used with care. 
     
    Notify means all processes sensitive to this event are made runnable. The process in your case is sensitive to the event when its execution reaches the wait instruction. When the notify instruction is executed before the wait instruction is reached, no process is sensitive to the event. Event notifications are not stored for later waits. 
    Assume the following example:
    p1(){ wait(ev1); cout << "wait done"; } p2(){ ev1.notify(); } When p1 starts first, it executes until wait is reached. Then p1 is suspended and p2 continues. The notification of ev1 is executed, p1 is made runnable again, and the message is printed. 
    When p2 starts first, the notification of ev1 is done without any process waiting. Hence, it has no effect. Then p1 is started. It reaches the wait statement and will wait forever because the event notification has been executed before. No message will occur. 
    Since SystemC contains no guaranty about the order in which processes runnable in the same delta cycle are executed, a model like the example leads to non-deterministic behavior. 
     
    Greetings
    Ralph
  21. Like
    amitk3553 reacted to ralph.goergen in Events notifications and wait for events   
    Hi.
     
    p1 and p2 run logically in parallel, so you actually don't want to rely on a specific execution order. 
     
    You can avoid this situation by not using notify with no parameter (immediate notification). 
    Use notify(sc_core::SC_ZERO_TIME) instead to schedule the event in the next delta cycle. 
     
    At the end of delty cycle 1, p1 definitely reached the wait instruction and the event in delta cycle 2 triggers p1 to continue. 
     
    Greetings
    Ralph
  22. Like
    amitk3553 reacted to mohitnegi in Socket for Transceiver   
    hy KS,
     
    In refernce to section 13.2 of LRM
     
     
     socket which i understood is can have both forward and backward path but i am not sure whether full duplex is possible ..
    May be other could help ...
     
    An option i would suggest  in systemC is to make a bidirectional sc_port(inout) and use it ...
    Note- benefits of sockets wont be there as mention in the same section ...
  23. Like
    amitk3553 reacted to Philipp A Hartmann in xor operation   
    Cam,
     
     
    Why do you call the operation "xor reduce"?  A bitwise "xor" operation has the same number of bits as its operands.
    Have you tried the (C++) operator "xor"?
    unsigned int a = 42; unsigned int b = 21; unsigned int c = (a xor ; // or in short notation (a ^ An "xor reduce" operation as provided by the SystemC datatypes would be defined on a single operand and return a single bit after applying the "xor" bit by bit.  This is not defined for the built-in C++ datatypes.

    hth,
      Philipp
  24. Like
    amitk3553 got a reaction from Annossyenudge in Type casting and concatenation   
    Hello,
     
    I faced problem in concatenation. I am able to concatenate sc_bv<8> type arguements, but not int type ??
     
    a = (b,c); //where b and c are of sc_bv<8> type
     
     
    I tried following also, compilation errors are there
    cmd_opcode.write( concat(cmd_op_msb.read().range(7,0), cmd_op_lsb.read().range(7,0)) );  
    cmd_opcode = concat(a, ab);  
     
    Next I tried to typecast sc_bv<8> into int type, i tried in following ways, but its not happening, showing compilation errors??
     
    cmd_opcode = (int) cmd_opc; //where cmd_opc is of sc_bv type 
    cmd_opcode.write(static_cast(cmd_opc.read()));
    cmd_opcode.write(cmd_opc.read().to_int());
     
     
    Please throw some light on these !!
     
    Regards
    cam
  25. Like
    amitk3553 got a reaction from Annossyenudge in Pass Parameter   
    Hello,
     
    In comments there are questions, answer please...Actually I have to pass parameter from the top.
     
    #define test testcase_001     //have to pass parameter, is this right way? 
    #include "testcases/test.cpp"   //could I pass parameterized value here?

    class hci_test
    {
       public:
       unsigned char* host_hci_pkt_arr;
       unsigned int address;
       test test_case;                       //could I make object handle like this(using parameter here)??
       hci_test()                                //constructor
      {
         host_hci_pkt_arr = new(nothrow) unsigned char [20];
         host_hci_pkt_arr[0] = test_case.host_hci_pkt_arr[0];     
         host_hci_pkt_arr[1] = test_case.host_hci_pkt_arr[1];
      }
    };       
    After compilation 
    compiler throwing errors

    :2nd line: error: testcases/test.cpp: No such file or directory

    :9th line: error: ISO C++ forbids declaration of ‘testcase_001’ with no type

    :9th line: error: ISO C++ forbids declaration of ‘test_case’ with no type   and when I comment first line of code and in 2nd and 9th line, instead of test, I write testcase_001, then it works fine means problem is in passing value from the top.   So let me know the corrections required in it if any or some other way to achieve this kind of passing parameters or values from the top, as #define is just used for aliasing or can do the work like parameter? Please respond   Thanks
    cam
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