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  1. Hi Can we force signals through the backdoor register access of data_type net. How can we read/write these signals through the hierarchical model. Please let me know the procedure.
  2. Can some-one explain how to specify in uvm-ral the syntax for hdl_path in a backdoor register access. How are the field names and registers arranged
  3. Hi, Can anyone explain what a Backdoor register access ? A backdoor access uses the simulator database to access the register bits. What is this simulator database and how it is created ?
  4. Thanks for procedure. Do we need to add any flags/options when we include the uvm_pkg.sv
  5. Hi, I am using VCS tool which has UVM 1.1 verison. I want to override this verison of uvm with the UVM 1.1c obtained from Accellera. Please let me know if this is possible and also please let me know the procedure Thank you
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