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phil

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  1. Hi Daave: Thanks for the explanation. It makes sense now. --Phil
  2. interesting. it is an error only when func() uses "ref" of obj1. below is the complete code. please note that function pa() uses "ref A". Without "ref", the code works. With "ref", the error message is: pa(this): invalid ref argument usage because actual argument is not a variable. [systemVerilog]. Why "this" can't be used as an argument of a object reference? package my_pkg; class A; parameter bit base_a = 1; endclass // A function automatic void pa(ref A tr); $display("pkg tr.base_a %h", tr.base_a); endfunction // pa endpackage // my_pkg `include "my_pkg.svh" import my_pkg::*; class sub_a extends A; function new(string name="sub_a"); pa(this); endfunction // new endclass // aub_a module try; sub_a sa; initial begin sa = new; end endmodule
  3. Hi: is there a way to pass "this" (or other means that represent the calling object handle) as an argument to a function, in SystemVerilog? Here is this unexpected situation: There is a function: func(class1 obj1, class2 obj2); inside class1, there is a function foo(), calling func(). Class1::foo(); void' func(this, obj2); endfunction But surprisingly to me, it is illegal, because "this" is not a variable, as told by the compiler. So is there a way to pass the handle of the calling object as an argument to a function? if not, is there a work around? Thanks phil
  4. Hi: UVM_REG provides memory burst access routines, but no register block burst accesses. for some bus protocols, they are different types of transactions between register burst access and a sequence of consecutive single register accesses. If I need to test the burst transactions on a register block, what would be a good approach? I am thinking implementing block busrt access routines by modifing memory burst routines. Thanks.
  5. Thank you all for your responses. The ideas and explanations are really helpful. I will go ahead and impelment one of them.
  6. This certainly works. But somehow it seems non-uvm-ish to me. Since I am new to UVM, I am trying to learn the recommended UVM way first, before becoming creative. Is above a typical way to automatically randomize delay between register_model transactions? Thanks. Phil
  7. I am trying to figure out a way to insert random delay between regmodel transactions, but couldn't find any facility in UVM_REG that support this. Could anyone share some insights about how to approach this? Thanks for the help. Phil
  8. Hi: I can see that register layer model is very helpful in testing registers. But I am not sure how to use it in other functional tests that require lots of control register read/write to generate/control the transactions. Has anyone done this in real projects? if so, do you have to re-write your existing sequences? Thanks.
  9. Hi: I am trying to incorporate register model into our test environment, but not even sure if I am on the right path. Let's say I have a sequence item for data transaction with a property, xfer_size, which corresponds to a control register field. In old days, this sequence item would be passed down to individual bus drivers and the drivers would find the address of those properties (forexample, xfer_size => address 32'h00a0, field mask 32'h00ffff) and carry out the register access. Now after we create register models, the xfer_size corresponds to "ctlr.mod1.ctl.xfer_size". What is the typical way for bus driver to use this register model to access it? I am thinking the driver would have to somehow translate req.xfer_size to "ctlr.mod1.ctl.xfer_size", then do reg_field.write(), with the help of an adapter, etc. But it seems quite involved. Am I on the right path? If so, how should the translation be done? Thanks.
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