Jump to content

mrforever

Members
  • Posts

    118
  • Joined

  • Last visited

Everything posted by mrforever

  1. Hi, adiel Thanks for your seguestion. I have tried that way, but it appeared that there wasn't any active phase in the phase debugger pane. But the reports above [PH/TRC/SCHEDULED] Phase 'common.run' (id=121) Scheduled from phase common.start_of_simulation implies that the procedure should have reached the start_of_simulation phase. I suppose that there should be active end_of_elaboration phase or active start_of_simulation phase. I don't know why there was not any active phase. By the way, how can I see the active sequences? Regards mrforever
  2. Hi, adiel i have found that i would have installed the *amd64.tar. thanks very much Best Regards mrforver
  3. Hi, Peer Mohammed I have added the options "-full64 -debug_all -picarchive" after restalling vcs(install *common.tar *amd64.tar and *linux.tar), it still didn't work. but i cann't get the information vcs runtime internal error now, the procedure is just stuck at the line: UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'uvm' (id=170) Starting phase Does it mean that i should trace the uvm_phase mannualy? Best Regards mrforver
  4. Is there anybody having encountered the same problem? Thanks very much!
  5. I have added the option "-debug_all" and "-picarchive", it didn't work. When i used the option "-full64" it reported as follow, ERROR - /EDA_Tools/synopsys/vcs1209/amd64/bin is not valid directory, is VCS_HOME set correctly? make: *** [comp] Error 255 $VCS_HOME=/EDA_Tools/synopsys/vcs1209, i think it is right. And I find that there isn't any */amd64/ sub directory in directory /EDA_Tools/synopsys/
  6. Hi, all experts i met one runtime error as follow. The option "+UVM_PHASE_TRACE" added is used to trance the uvm_phase. It seems like being stuck in some uvm_phase and then generates the vcs runtime internal error? Could anybody give me some clue? Thanks in advance. Command: ./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log Chronologic VCS simulator copyright 1991-2012 Contains Synopsys proprietary information. Compiler version G-2012.09; Runtime version G-2012.09; Dec 26 12:19 2012 ---------------------------------------------------------------- UVM-1.1c © 2007-2012 Mentor Graphics Corporation © 2007-2012 Cadence Design Systems, Inc. © 2006-2012 Synopsys, Inc. © 2011-2012 Cypress Semiconductor Corp. ---------------------------------------------------------------- *********** IMPORTANT RELEASE NOTES ************ You are using a version of the UVM library that has been compiled with `UVM_NO_DEPRECATED undefined. See http://www.eda.org/svdb/view.php?id=3313 for more details. (Specify +UVM_NO_RELNOTES to turn off this notice) UVM_INFO @ 0: reporter [RNTST] Running test test_config... UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common' (id=55) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common' (id=55) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.build' (id=73) Scheduled from phase common UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.build' (id=73) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.build' (id=73) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.connect' (id=85) Scheduled from phase common.build UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.connect' (id=85) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.connect' (id=85) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.end_of_elaboration' (id=97) Scheduled from phase common.connect UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.end_of_elaboration' (id=97) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.end_of_elaboration' (id=97) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.start_of_simulation' (id=109) Scheduled from phase common.end_of_elaboration UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.start_of_simulation' (id=109) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.start_of_simulation' (id=109) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.run' (id=121) Scheduled from phase common.start_of_simulation UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm' (id=170) Scheduled from phase common.start_of_simulation UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.run' (id=121) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'uvm' (id=170) Starting phase Command line: ./simv./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log Command line: ./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log --- Stack trace follows: No context available VCS runtime internal error (core dumped) . Please contact vcs_support@synopsys.com or call 1-800-VERILO
  7. Hi, all experts i met one runtime error as follow. The option "+UVM_PHASE_TRACE" added is used to trance the uvm_phase. It seems like being stuck in some uvm_phase and then generates the vcs runtime internal error? Could anybody give me some clue? Thanks in advance. Command: ./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log Chronologic VCS simulator copyright 1991-2012 Contains Synopsys proprietary information. Compiler version G-2012.09; Runtime version G-2012.09; Dec 26 12:19 2012 ---------------------------------------------------------------- UVM-1.1c © 2007-2012 Mentor Graphics Corporation © 2007-2012 Cadence Design Systems, Inc. © 2006-2012 Synopsys, Inc. © 2011-2012 Cypress Semiconductor Corp. ---------------------------------------------------------------- *********** IMPORTANT RELEASE NOTES ************ You are using a version of the UVM library that has been compiled with `UVM_NO_DEPRECATED undefined. See http://www.eda.org/svdb/view.php?id=3313 for more details. (Specify +UVM_NO_RELNOTES to turn off this notice) UVM_INFO @ 0: reporter [RNTST] Running test test_config... UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common' (id=55) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common' (id=55) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.build' (id=73) Scheduled from phase common UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.build' (id=73) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.build' (id=73) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.connect' (id=85) Scheduled from phase common.build UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.connect' (id=85) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.connect' (id=85) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.end_of_elaboration' (id=97) Scheduled from phase common.connect UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.end_of_elaboration' (id=97) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.end_of_elaboration' (id=97) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.start_of_simulation' (id=109) Scheduled from phase common.end_of_elaboration UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.start_of_simulation' (id=109) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.start_of_simulation' (id=109) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.run' (id=121) Scheduled from phase common.start_of_simulation UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm' (id=170) Scheduled from phase common.start_of_simulation UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.run' (id=121) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'uvm' (id=170) Starting phase Command line: ./simv./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log Command line: ./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log --- Stack trace follows: No context available VCS runtime internal error (core dumped) . Please contact vcs_support@synopsys.com or call 1-800-VERILO
  8. i have solved the problem when i change the name duv_if to duv_vif. but i still have one question. how does uvm_config_db::set() and uvm_config_db::get() do the type match in the case of that duv_vif is not a virtual interface in testbench while duv_vif is virtual interface in class chpp_env. Will uvm ignore the virtual keyword when it does the type match using uvm_config_db?
  9. i got it, maybe i should change the name duv_if to duv_vif. thanks, Merry Christmas, ajeetha.cvc
  10. Oh, my god! Forget today is Christmas day! The problem will sink unfortunately! Sadly...
  11. Hi, all experts I met such a UVM_FATAL when i compile the codes as follows. file1: interface chpp_sigif; ... endinterface: chpp_sigif file2: class chpp_env extends uvm_env; // Virtual Interface variable protected virtual interface chpp_sigif duv_vif; ... function void build_phase(uvm_phase phase); ... if(!uvm_config_db#(virtual chpp_sigif)::get(this, "", "duv_vif", duv_vif)) begin `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".duv_vif"}); end ... endfunction ... endclass: chpp_env vcs(Version: G-2012.09) reports such a UVM_FATAL as follows: UVM_INFO @ 0: reporter [RNTST] Running test test_config... UVM_FATAL ../sv/00_top/100_chpp_env.sv(73) @ 0: uvm_test_top.env [NOVIF] virtual interface must be set for: uvm_test_top.env.duv_vif --- UVM Report Summary --- ** Report counts by severity UVM_INFO : 1 UVM_WARNING : 0 UVM_ERROR : 0 UVM_FATAL : 1 ** Report counts by id [NOVIF] 1 [RNTST] 1 $finish called from file "/EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_report_object.svh", line 277. The UVM_FATAL says that virtual interface must be set for: uvm_test_top.env.duv_vif. But duv_vif is already the virtual interface. And i open the file "uvm_report_object.svh" but cann't find any clue. Will it be the problem of uvm-1.1c library which is downloaded from the sites http://www.accellera.org/downloads/standards/uvm ? The other information reported by vcs *********** IMPORTANT RELEASE NOTES ************ You are using a version of the UVM library that has been compiled with `UVM_NO_DEPRECATED undefined. What's the purpose defining the macro `UVM_NO_DEPRECATED? Could any expert explain my question? thanks very much.
  12. Oh, stupid mistake. It became okay changing rw to reg_rw.
  13. Hi, all I met the compile error when i use the uvm_reg_adpater. Could someone help to solve. Here are the codes: `ifndef __CHPP_REG2PCIE_ADAPTER__ `define __CHPP_REG2PCIE_ADAPTER__ //------------------------------------------------------------------------------ // // CLASS: chpp_reg2pcie_adapter // //------------------------------------------------------------------------------ class chpp_reg2pcie_adapter extends uvm_reg_adapter; // provide implementations of virtual methods such as get_type_name and create `uvm_object_utils(chpp_reg2pcie_adapter) // functions and tasks function new(string name = "chpp_reg2pcie_adapter"); super.new(name); endfunction virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op reg_rw); chpp_pcie_item bus = chpp_pcie_item::type_id::create("reg_rw"); if (reg_rw.kind == UVM_READ) begin bus.req_typ = MRd; bus.length = 0; bus.reqer_id = cpu_id; bus.last_be = 0; bus.first_be = 0; bus.addr = reg_rw.addr; bus.data_payload.size() = 0; end if (rw.kind == UVM_WRITE) begin bus.req_typ = MWr; bus.length = 1'b1; bus.reqer_id = cpu_id; bus.last_be = 0; bus.first_be = 0; bus.addr = reg_rw.addr; bus.data_payload.push_back(reg_rw.data); end return bus; endfunction virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op reg_rw); chpp_pcie_item bus; if (!$cast(bus,bus_item)) begin `uvm_fatal("NOT_REG_TYPE","Provided bus_item is not of the correct type") return; end if (bus.req_typ == MRd) begin reg_rw.kind = UVM_READ; reg_rw.addr = bus.addr; reg_rw.data = bus.data; //reg_rw.byte_en = bus.byte_en; reg_rw.status = UVM_IS_OK; end if (bus.req_typ == MWr) begin reg_rw.kind = UVM_WRITE; reg_rw.addr = bus.addr; reg_rw.data = bus.data; //reg_rw.byte_en = bus.byte_en; reg_rw.status = UVM_IS_OK; end endfunction endclass : chpp_reg2pcie_adapter `endif VCS1209 reports such error: Error-[XMRE] Cross-module reference resolution error ../sv/02_master/config/221_chpp_reg2pcie_adapter.sv, 64 Error found while trying to resolve cross-module reference. token 'rw'. Originating package 'chpp_pkg'. Source info: if (rw.kind == UVM_WRITE) begin bus.req_typ = MWr; ... 15 warnings 1 error CPU time: 2.863 seconds to compile Thanks in advance!
  14. Hi, SV experts Can SV detect integer variable's changing? if have the code like this, integer a; @(a) begin do_function0 ; end do_function1; how does it behave? will it execute do_function0 when "a" changes, while execute do_function1 when “a" doesn't change ? thanks for the answer.
  15. hi, experts If i wish to define a custom comparison for my transaction, i can do it as these two ways. 1) override do_compare in my transaction class, and use the uvm_in_order_comparator . 2) pass in a policy class, which includes a static comp method that returns a bit, to the comparator that defines my custom comparison. i know how to implement it using the second way. but i don't know how to use uvm_in_order_comparator. i have tried to found it in this forum and uvm class ref, but i couldn't find any piece of examples, would somebody give some examples about using uvm_in_order_comparator. for example, how does uvm_in_order_comparator invoke compare() , which invokes do_compare() in uvm automatically.
  16. hi , experts Can one scoreboard have multiple uvm_analysis_imps which transfer the same kind of items. Image such a situation, the scoreboard have two uvm_analysis_imps, one of which receives items from reference model, the other receives items from monitor. If it is okay, then how implement different two write(T=items, Type=parent class) methods in scoreboard in the case of that it needs to treat the items differently? by the way, the parameter "parent class" of the uvm_analysis_imps are both scoreboard. thanks in advance.
  17. Hi, experts there are many phases in uvm, some of which are function phases and others are task phases. function phases don't need simulation time while task phases need. now i establish one reference model which extends from uvm_component. i want to generate expect items in the main_phase in reference model, and the process of generating expect items cann't spare any simulation time. will this way be okay if i don't add any simulation time or process sparing simulation time manually in the main_phase, which is one kind of simulation time phase ? thanks in advance.
  18. Hi, i saw "uvm_blocking_peek_imp#(ubus_transfer,ubus_slave_monitor) addr_ph_imp" in ubus_slave_monitor.sv file. but i don't know how it peeks the ubus_transfer, i cann't see any other code about addr_ph_imp except in class ubus_slave_agent like this: sequencer.addr_ph_port.connect(monitor.addr_ph_imp); i guess that there should be some codes like this addr_ph_imp.write(ubus_transfer), then the sequencer can peek the ubus_transfer, but there isn't. any expert to answer my question? thanks in advance.
×
×
  • Create New...