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  1. Axel Scherer manages a team of UVM-ML (e and SystemVerilog) experts and has recently posted 24, very short, byte sized UVM-e basic tutorials. Check them out. These e-based videos are targeted for design and verification engineers who are interested in learning about the basic concepts of UVM-e and the benefits that the e language provides. As you may know, e is an IEEE 1647 standard hardware verification language (HVL) that is tailored to implementing highly flexible and reusable verification testbenches, leading to a significant productivity improvement. Cadence has implemented UVM in e to make it easier for e and SV users to work together. These videos provide the basics of Aspect Orient Programming (AOP) capabilities, constrained randomization, scoreboarding, etc.... So, relax, make yourself comfortable and enjoy these videos. Hopefully, these videos will excite you enough to try out the e language on your new or existing verification project. Here's a list of You Tube e videos for your enjoyment! http://www.youtube.com/playlist?list=PL69F243C52B24EF60&feature=plcp The Initial set of topics include the following: 1. Introducing UVM 2. Example DUT 3. UVM Environment 4. Interface UVC 5. Collector 6. Monitor 7. Sequence Item 8. Sequence 9. BFM 10. Sequence Driver 11. Agent 12. Agent types 13. Interface UVC environment 14. Virtual Sequence Driver - Sequence 15. Module UVC 16. Scoreboard 17. DUT Functional Coverage 18. Testbench 19. Test 20. Configuration 21. AOP - Aspect Oriented Programming 22. Phases 23. Objections 24. Signal Maps = Kishore Karnane Cadence Verification Product Director
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