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  1. i know polymorphism, but perhaps you didn't get my question base class handle can point to derived class handle but not vice versa (with one exception) $cast(local_seqr, m_sequencer) here its derived class handle pointing to parent m_sequencer handle. may be i am missing another basic thing.
  2. thanks dudi, In my above post i mentioned that $cast as listed also works. Can you please explain me how ? ""$cast( local_seqr, m_sequencer) and it works, but i dont understand how local_seqr derived class sequencer handle can be pointed to m_sequencer handle which is base class handle and pointing to base uvm_sequencer in uvm.""
  3. hi experts, Please help me figure out this. Also please pardon the syntax. Just trying to write the logic here. 1) i have class my_seqr derived from uvm_sequencer; class my_seqr extends uvm_sequencer; 2) class my_sequence_item derived from uvm_sequence_item; Now in agent i have created the sequencer using create method. class my_agent extends uvm_agent; my_seqr seqr; seqr = my_seqr::type_id::create("seqr") // ignore syntax please The problem is, inside my_sequence_item i want to point to "seqr" object. How can i do this. example: class my_sequence_item extends uvm_sequence_item; my_seqr local_seqr; now i want local_seqr to point to seqr in agent class. I know m_sequencer handle to uvm_sequencer is there in UVM, but that is for uvm_sequencer class and not for my_seqr derived class. To be honest one of my friends did this: $cast( local_seqr, m_sequencer) and it works, but i dont understand how local_seqr derived class sequencer handle can be pointed to m_sequencer handle which is base class handle and pointing to base uvm_sequencer in uvm. Am i missing something in how m_sequencer works ? Please help. much thanks.
  4. hi Whiteriver, Thanks a lot for your feedback. I am really thankful to you for your time in going through my big big post and answering all my Qs. I was of great help. thanks.
  5. hello Tfitz, Thanks a lot for your feedback. Actually, i was not aware of sequence layering. I thought there can be multiple sequences running in parallel or in sequence and there can be library of sequences. I am re-iterating my requirements here at a very top level and keeping it simple. 1) Data class to form data items 2) data schedular to build 9 queues of different data items and depending on the rate specified by user for each indiviual data type. 3) packet class defining packet structure. 4) packet formatter, forming packets from 9 queues of data types in item 2 above and sending the WHOLE packet to driver. So from UVM from what i know so far, i thought of having. 1) data as sequence item 2) data scheduler as sequence item 3) packet as sequence item 4) embedding packet formatter logic inside sequence item class, which will form the packet and have all raise and drop objections stuff. and also sent to drive with `uvm_send Now if i take CHANNEL as in VMM, then the equivalent of UVM i was not able to think. Here was problem i was facing. 1) data as sequence item, data scheduler as sequence item. 2) packet as sequence item. Now the packet has to go to driver, so in sequence class i would have: class packet_sequence extends uvm_sequence #(packet) but then i was not able to think, where would be the packet formatter logic, which will form the packet and put it in a channel Where would this channel be ? and how can a packet_sequence class extract the packet from this channel and sent it to the driver. Those were the things not clear to me and hence i thought on the lines that i listed in post before. As you suggested that, there could be sequence layering. Please expain a bit on how it would fit in my code and yes please point me to the info. At learning stage any information is helpful. thanks a lot, appreciate your time.
  6. Thanks a ton, Whiteriver for your prompt reply. Thanks. After a daylong thinking, I have come up with following logic. Please provide your feedback and let me know if I am thinking right, anything that I might be missing. Also I do have some doubts about the code. I have asked Qs in RED along with my thinking process. /******** C1 -- data classes ***********/ 1) Consists of all the constraints of what contents each data type D0-D8 should contain, and weight distribution given to each data type. Also consists of covergroups. 2) Base class derived from uvm_sequence_item; ---------------------------------------------- /******** C2 - data rate scheduler class ******/ 1) This class should be derived from where ???? uvm_sequence_item ?? Should I derive this class from uvm_sequence_item, even though it is not a data type ?? 2) Factory create 9 queues for each of data types D0-D8 Using factory create method, is this right way ?? 3) Implements rate scheduling logic along with constraints to generate data types based on user defined values and pushes them to their respective queue. 4) Also implements logic on extracting back data types from their respective queues. 5) In post_configure phase enable rate_schedular, call randomize (), so that it randomizes the data items and constraint are applied. At this point it will start generating data types. What should I do so that every time data items are generated they are randomized and proper constraints are applied. Would single call to randomize() work ??------------------------------------------- /******** C3 - packet class *************/ 1) Class packet extends uvm_sequence_item; 2) Factory create array of type data class of size 8, to fit in 8 consecutive data types in packet 3) Consists of random flags for different types of packet corruption 4) Constraints and cover groups of the order of how data types D0-D8 should fit in packet. 5) Function to add data type to packet “add_one_data†------------------------------------------- /********** C4 – sequence class **************/ `include C1, C2, C3 // include all classes: data, data scheduler, packet classes 1) Class packet_sequence extends uvm_sequence # (packet); 2) Include random variables and constraints to specify how many data types 0-8 a packet should contain. And also constraint weights for each type of data types D0-D9 in packet. 3) Factory create data rate scheduler class 4) Virtual task body(); // Are below steps looking OK or I am missing something ?? // How do I make sure that packet class random variables are randomized() and proper constraints are applied. // raise objection while (not_done) // flag to indicate that keep going till all data type generation is done. `uvm_create (req); // 1** do checks here that ipg delay has been met, // 2 ** also check that there are enough data items in the data queues // wait here till 1 and 2 ** are not met for(int i=0; I <8; i++) begin packet.add_one_data(D0-D8); end `uvm_send(req); end// while // drop objection ---------------------------------------------- Please provide any comments that you might have regarding the logic Does above logic ensures that each random variable declared in all classes above will be randomized and proper constraints applied to classes ?? thanks a ton for your help.
  7. Hi there, Please help me on this problem. I am still learning UVM. I have transaction type "Packet", which is generated by combining different data types like for example Packet = {D0, D8, D7, D1, D1, D7,D0,D8} where D0, D8, D7, D1 are different data types derived from same base class. Packet is formed when there are 8 such data types available and generation of all these data types is controlled by RATE SCHEDULER specified by user. At very low rates, packets will be formed after long time. At times there many not be any Data type, and hence no packet can drive to driver. In VMM it was easy, whenever Packet was formed, i would push it to driver by using channel. Else nothing is driven. In UVM, i am not getting how to do. Below, how should i write body task. 1) I can't have specific number in repeat () because packets are generated on fly by the scheduler. 2) I can't have packets in queue [$], and use for loop in task body, because queue size will keep on changing. 3) What will happen if i call uvm_do(req) macro, but there is no actual packet formed at that point. class packet_sequence extends uvm_sequence #(packet); /// taking out new function etc virtual task body(); // raise objection repeat(10) begin <----------------- `uvm_do(req); end // drop objection Please help me in understanding a bit. thanks.
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