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  1. Agreed, of course, but that's just one of the mechanisms for specifying common test behaviour (another being, for example, a base test class, or classes, that do the same thing). I was more curious about running a sequence on a sequencer through the default sequence hook vs. explicitly starting it in some common code. Doing it explicitly feels like it produces more obvious and readable code vs. what feels like a back door way of getting a sequence started, no?
  2. Yeah, that's exactly what I'm doing. Now, is there some advantage of using default_sequence instead of explicitly creating and starting one from the test? I've seen someone write that one should always use default sequences, but I couldn't find any explanation as to why he felt that way..
  3. Thanks for the replies! I wanted to run an init sequence in configure_phase of the base test. That way, the other tests don't have to explicitly call it, and their main_phase starts automatically after the init is done. That makes sense from a logical point of view, but how does that fit into UVM phasing? I.e., since the drive is a component, it also has the configure, run, etc. phases, so how do I make one thread that runs through all of those phases? I have to put the "get_next_item / drive / item_done" loop into some phase, no?
  4. Perfect! Totally missed it in the docs... Thanks, I knew there had to be something in there.
  5. I'd like to perform an action every time something it put or removed into a uvm_tlm_fifo inside my component. Is there a way to register a "pre_put" or "post_put" or some other callback to accomplish this? I can't find anything like that in the documentation, which makes me believe that I would have to extend the class and implement that myself, right?
  6. My understanding is that, logically, run phase is just forked off in parallel with the new phasing system... I have two questions regarding this: 1) How does one work in a mixed environment where some components are using run_phase and others are using new phases? Run phase seems to end as soon as all components using run_phase are not objecting, even though some new components are running, say, configure_phase. Shouldn't run_phase run until all of new run phases have completed? Is there an easy way for me to do this? 2) I have a driver that drives transactions in both configure and main pha
  7. I have a third-party SVA interface checker that I can't modify... It will report errors when interface protocol is violated, but my "UVM world" is oblivious to it and will report the test as passing as no UVM component reported an error. Is there a way to "catch" the SVA assertions firing and react to them from within UVM, without modifying the SVA checker?
  8. This is a question from a newbie, so I apologize if this is a dumb question. On the bus I'm working on, the slave is trivial -- it has a bunch of inputs, but the only output is a 'ready' signal, indicating that the slave is ready to receive a command. Creating a driver / sequencer / sequences / transaction to toggle one signal seems like an overkill, but on the other hand, I want to be able to control how the ready signal behaves from within a test. Should I go with the full transaction approach, or just write some configuration values directly into the driver that will then have a few toggle
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