So I have a standard testbench with a packet "fast path" and a processor "slow path". Basically, the processor agent will get a test_configuration sequence started on its sequencer during the UVM configure_phase. The packet agent will then get a data sequence started on its sequencer during the main_phase, and then the processor agent has a check_results sequence started during a later taskable phase. So far so good.
We are now trying to inject "packets" into the data stream from the processor path during this "main phase". I am a little baffled over the best way to handle this and stay inside the UVM framework.
I can create a processor sequence which creates my packet sequence items (randomly. Packet transactions are in the processor sequence-- ie. composition), and then use the processor commands to inject into the packed packet into the data stream. This works well.
The problem I am running into is how do I get those randomly generated packets from my processor sequence over to the scoreboard. My scoreboard is receiving the "actual" data just fine from the packet monitors on an analysis port, now I just need to get this randomly generated data contained in my processor sequence into the "expected" analysis port.
The sequence is created in the main phase and then started on the processor sequencer then-- so it doesn't exist at the beginning of time-- so I cannot use connect on any analysis ports within the sequence itself (if that is even possible). I tried using an m_sequencer call to write to a uvm_analysis_port there that I could connect-- and that compiles but when I run; at time zero it tells me that it cannot find the analysis port...
uvm_analysis_port #(phyLayerControlInfo) messagePort; // declaration
under build_phase-- after super.build
message_port = new("message_port", this);
Within the sequence task body...
No field named "message_port"
Am I approaching this the correct way? This has to be common-- how are others doing this?