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wpiman's Achievements


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  1. If anyone is following this thread-- I am using UVM 1.1A. I tried jumping from post_shutdown back to configure. That was all fine. This issue there was the run_phase ends when post_shutdown ends. I now jump from the shutdown phase and everything seems to operate as expected.
  2. Thanks. I was looking to do this. I see some odd behavior from my testbench I am having a hard time explaining-- but overall it seems to be working.
  3. continued: I would connect the analysis port up if I could access the messagePort. I have not got that far yet. I used the p_sequencer port on the sequencer by using the uvm_declare_p_sequencer macro and I am getting past the error message. I am still not convinced I am approaching this in the ideal way. Edit: this is all working very well now. Thanks.
  4. I do use the monitor to generate the "expected packets" on the incoming packet bus and well as the "actual packets" on the outgoing packet bus. What I am trying to do is determine if the processor bus injected a packet into the fast path. I suppose I could monitor the processor write and read transactions to determine that. I had not thought of that. It adds another layer of complexity-- ie. I'd have to monitor the processor read/write cycles and generate packets on an analysis port.
  5. So I have a standard testbench with a packet "fast path" and a processor "slow path". Basically, the processor agent will get a test_configuration sequence started on its sequencer during the UVM configure_phase. The packet agent will then get a data sequence started on its sequencer during the main_phase, and then the processor agent has a check_results sequence started during a later taskable phase. So far so good. We are now trying to inject "packets" into the data stream from the processor path during this "main phase". I am a little baffled over the best way to handle this and stay inside the UVM framework. I can create a processor sequence which creates my packet sequence items (randomly. Packet transactions are in the processor sequence-- ie. composition), and then use the processor commands to inject into the packed packet into the data stream. This works well. The problem I am running into is how do I get those randomly generated packets from my processor sequence over to the scoreboard. My scoreboard is receiving the "actual" data just fine from the packet monitors on an analysis port, now I just need to get this randomly generated data contained in my processor sequence into the "expected" analysis port. The sequence is created in the main phase and then started on the processor sequencer then-- so it doesn't exist at the beginning of time-- so I cannot use connect on any analysis ports within the sequence itself (if that is even possible). I tried using an m_sequencer call to write to a uvm_analysis_port there that I could connect-- and that compiles but when I run; at time zero it tells me that it cannot find the analysis port... in sequencer.... uvm_analysis_port #(phyLayerControlInfo) messagePort; // declaration under build_phase-- after super.build message_port = new("message_port", this); Within the sequence task body... m_sequencer.message_port.write(messageToSend); Error: No field named "message_port" Am I approaching this the correct way? This has to be common-- how are others doing this?
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