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kirloy's Achievements


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  1. For design using UVM from separate library -profiler_all must be used for asim command instead -profiler. -profiler collects data only for working library code. Other code in this case represents code from libraries other than work - in this case from UVM. When you use -profiler_all then code from all libraries used in simulation is profiled. If UVM needs to be profiled this is also good idea to use debug version of UVM (compile UVM with -dbg switch and use library created this way)
  2. Some issues with "other code" was fixed in newest Riviera 2015.10. Please try it.
  3. Have you tried to add uvm_resource_options::turn_off_auditing() before run_test. UVM collects lots of data which is not needed when you do not debug. In certain cases - when you have lots of uvm_resource data base accesses - then it can consume lots of memory. You design can start some activities later on during the tests which may slow down simulator - as it has much more to simulate - ie first test doeas all configuration and then it starts do some transission. Anyway profiler results should give you some clues you are just blind when not looking at it. ie you can run till the point where it is fast see what is on the profiler top on - then run full - see if smth changed. If you have issues with profiler reports analysis you may always consult them with technical support. Finally it can be tool bugs in this case also only support can help you.
  4. You can have procedures proc mydo {arg} { global RUNNING_SCRIPT_NAME set RUNNING_SCRIPT_NAME $arg do $RUNNING_SCRIPT_NAME } proc whatami {} { global RUNNING_SCRIPT_NAME echo $RUNNING_SCRIPT_NAME } And then run yours script: mydo 2.do
  5. @puneet I would not call it a tool bug it is rather interpretation issue. For me const class is not the same as ref const class. Some users may find tool behavior described by Tudor as an advantage.
  6. Yours example is legal according to latest LRM. Probably some vendors have not implemented this feature according to 1800-2012 yet.
  7. interface Inter (input logic clk); logic a; endinterface module A(); logic clk; Inter inter(clk); endmodule module B(Inter inter); always_ff @(posedge inter.clk) ... endmodule module top; A a( ); B b( a.inter ); endmodule
  8. There is always a pair of phases in UVM with the same name. One act as implementation, 2nd as a node in uvm phase schedule graph You can obtain both see below I've modify part of yours example: function void end_of_elaboration_phase(uvm_phase phase); // get handle to run phase uvm_phase tmp; uvm_run_phase m_run_phase = uvm_run_phase::get(); $display("From handle in end_of_elaboration"); m_run_phase.print(); tmp = phase.find_by_name("run",0); $display("get phase node in end_of_elaboration"); tmp.print(); endfunction task run_phase(uvm_phase phase); // get handle to run phase uvm_phase _phase; uvm_run_phase m_run_phase = uvm_run_phase::get(); $display("From handle in run"); m_run_phase.print(); $display("From param in run"); phase.print(); $cast(m_run_phase , phase.get_imp); $display("get imp from param is equal to uvm_run_phase::get"); m_run_phase.print(); endtask
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