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bhunter1972

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    bhunter1972 got a reaction from Tyson in parsing using system verilog   
    SV isn't the best language to parse with, but Python is!  You should consider having your Python script output real SystemVerilog code that can then be loaded into the simulator instead.
     
    Consider:
     
    for (addr, data) in write_commands:    print >>sv_file, "   block.write_data('h%s, 'h%s);" % (to_hex(addr), to_hex(data)) etc.
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