overlapped implication vs logical AND. |-> vs. && in UVM SystemVerilog Discussions Posted January 7, 2016 · Report reply When used in a coverpoint, what is the difference between overlapped implication and logical AND? |-> vs. && cp_test : cover property ( @(posedge clk) disable iff (!resetn) A |-> B ); cp_test : cover property ( @(posedge clk) disable iff (!resetn) A && B ); ? A colleague asked me. It seems to me they are the same and the logical AND is more readable.