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Everything posted by ljepson74

  1. As used in the SystemVerilog LRM, 1800.1-2017.pdf, what is the difference between these two terms? The first seems well defined. The second, not so much. * time slot * time step Cliff Cummings/Sunburst Design wrote the following in CummingsSNUG2006Boston_SystemVerilog_Events.pdf: If that is correct, then it seems the term 'time step' has returned.
  2. Join a casual gathering of SystemVerilog users. 7pm. Wednesday 20th. Patxi's in San Jose. 3350 Zanker Road. SJ, CA 95134. (If joining us, please reply on the meetup website indicated below, as this is not a reserved room, but just some tables pulled together, with everyone covering their own bill.) Happy Holidays
  3. What is the intended use case for 'starting phase'?** Is it so that a test writer can determine if a sequence has been started, so they might conditionally do something like raising an objection? thanks **I use 'starting phase', instead of starting_phase, because that seems to be how it is referred to now (perhaps because it is protected now).
  4. Regarding: I would not say that a phase is required and I would not say it is not required. The uvm phases will be passed through in succession, as a simulation runs. I would simply say "they will happen". In a normal UVM flow, there is no way to make a phase not happen**. I think the question you want to ask is whether you, a user, or a test/testbench, needs to use the end_of_elaboration_phase (or any phase). The answer to that, is no. If you do not specify a function or task for the specific phase (and raise an objection if necessary), it will simply pass through. italiya
  5. Yes, thanks Dave. (I shouldn't assume everyone I've seen on here monitors all the threads.) Feedback from Victor (the creator of edaplayground) on the edaplayground forum:
  6. Doulos/Victor, any thoughts? Is your editor causing mischief and adding characters at the ends of lines? Dave, I see your point now. i.e. In edaplayground the error message seems to point to a space after the backslash. Thanks.
  7. EDAboard.com ? Is that a typo? You just mean my text editor, right? I confirmed that there is no extra character at the end of the line. (Note: the links above have been fixed.)
  8. Thanks, Tudor and Dave. *) I updated the urls, per Tudor comment. *) Aldec and Mentor simulators were the two that I did not use. I now tried Aldec on edaplayground and see that it works. Unfortunately, with regards to this SV feature, I'm not using either of these simulators. Can anyone confirm that neither Cadence nor Synopsys support this? (Well, I guess I've figured out that they don't, now that I have witnessed at least one simulator support it. Aldec's.) Thanks.
  9. A backslash can be used to extend a string literal onto the next line if "the new line is immediately preceded by a \ (backslash)." Section 5.9 of 1800-2012.pdf, the SystemVerilog LRM I don't think I have ever been able to get this work and w/o looking I seem to recall it has been in Verilog/SystemVerilog for a while. Can someone tell me if vendors support this and perhaps correct the code below on edaplayground? example from LRM: $display("Humpty Dumpty sat on a wall. \ Humpty Dumpty had a great fall."); See example here (on Sept 29, urls below are updated in response to Tu
  10. Thanks, Dave. To be clear, as I understand, "synchronize that process to the clocking block event" in this case means a call to @(my_play_if.cb1); Good. I'm moving to use such calls for the advancement of time (mostly in drivers and monitors/collectors), instead of calls like @(posedge my_play_if.clock); or @(posedge clk);. Can you provide a pseudo-code example of "interacting with clocking block inputs ##0 delays"? As I understand**, if there is a default clocking_block (and only if), we can use cycle delays (i.e. ## integral_number) and that will cause a wait for th
  11. Q1) I'd like confirmation that the following waits for a posedge of clk are identical. (The code it refers to is far below.) 1) @(posedge my_play_if.clock); or @(posedge clk); 2) @(my_play_if.cb1); Q2) I'd also like to confirm that input and output clocking_skew of a clocking block have no effect on the inputs of the interface. They only affect the inputs and outputs of that clocking block. I'm pretty confident about both of these and the SystemVerilog LRM seems clear, but I want to confirm while I am cleaning up some inherited code which is not currently working. Referenc
  12. Thanks, Alan. That wasn't it, but Synopsys got back to me: For VCS: vcs -ID For Verdi waveform viewer: verdi -envinfo | more
  13. How can I check which VCS version I am using, from a Linux command line? I don't want to run a sim to find this information. I am looking for smthg like "irun -version", but for VCS. Pre-post discovery: It looks like "vcs -help", among other things, shows the compiler version. Afaik, the compiler version and simulator version are the same. Right? Normally, I wouldn't ask that, but I see/know that some tools (or subsections of tools) don't move in lock-step for versions (like simulators and waveform viewers). (Posting here because I didn't easily find this i
  14. Thanks a lot, dave_59. Seeing those two (the inline and the constraint block) lined up like you did will help this stick in my head that they are the same syntax.
  15. How can I use "randomize() with" along with "inside", on the same line? Below is some code that solves the problem using >= and <=, but I'd like to use "inside". module top; class aclass; int index; function void get_latency; //assert (randomize(index) with {index inside {[1:5]}}) else begin //WHAT IS THE PROPER SYNTAX? //assert (randomize(index) inside {[1:5]}) else begin //WHAT IS THE PROPER SYNTAX? assert (randomize(index) with {index<=5; index>=1;}) else begin //WORKS $display("ERROR: We failed!"); $finish;
  16. Awesome. +2pts for Logger. Thanks a lot, that is great to know about. I'll be using it. re: Section 18.5.14 Soft constraints (from 1800-2012.pdf)
  17. Tudor/Tinku, Thank you very much. I had considered these following variations (and will now make doubly sure they're clear in my mind): //i) disable iff (write_valid) !$isunknown(write_data) //use disable iff for asynchronous disabling //ii) write_valid |-> !$isunknown(write_data) //Recommended //iii) !(write_valid && $isunknown(write_data)) //***See below I had not thought about synchronicity with regards to disable iff, so thanks a lot for enlightening me, Tudor. (***And in another post we discussed implication versus logi
  18. Consider the following code and the assertion to check for unknown data. If the code will change so that there will now be an array of valids and datas, what is the best way to change the assertion, so that for each valid, the corresponding data is checked.? Can I do it one line? (I had been considering using a generate statement around it.) module top; bit clk; logic write_valid; logic write_data; always clk = #5 !clk; initial begin clk=0; write_valid=0; #7; write_valid=1; #100; $finish; end as_showme : assert prop
  19. Yesterday, I learned that when randomize is called, all active constraints in the scope must be met ... even if you are passing a specific member as an argument to the randomize call. i.e. If you try to randomize a specific class member by passing it to the randomize call, like this: randomize(var2), all constraints in the scope of the randomize must still be met, even if they have nothing to do with the member being randomized. ***Someone please jump in if I phrased that poorly or am incorrect. In the below example there are two variables and a constraint on one. Uncommenting the li
  20. I needed to step thru an enum in a testbench today. As it took me a while to figure out how to do it, I post a small example here. I want to do it without making any assumptions of the values of the enums (values are the default type of int, in this case). Reference: SystemVerilog doc "1800-2012.pdf" Section 6.19 Enumerations module top; //typedef enum {alpha=0, beta=1, gamma=2, delta=3, epsilon=4} greek; //to show default assignments typedef enum {alpha, beta, gamma, delta, epsilon} greek; greek letters2; initial begin $display("****** Walk thru an enumeration example.
  21. When used in a coverpoint, what is the difference between overlapped implication and logical AND? |-> vs. && cp_test : cover property ( @(posedge clk) disable iff (!resetn) A |-> B ); cp_test : cover property ( @(posedge clk) disable iff (!resetn) A && B ); ? A colleague asked me. It seems to me they are the same and the logical AND is more readable.
  22. Nhat, Can you provide more details in your question? You want a monitor and scoreboard to be able to check that suspend and resume operations occur correctly for a flash memory design. Correct? I would guess that few people on this forum are familiar with flash memory controller design and with those operations. I am not familiar with them. How about if you separate the application specific part (flash controller) of your question from the UVM/SV part? I think the flash part of the question confuses and deters people from responding. Your question was very short and provided l
  23. Yes. And I suppose there is no reason it should be a uvm_component - I am not using phases or anything particular to uvm_components here. I am probably muddying the waters by having "config" in the name, and will do some more reading today to understand normal UVM configurations. "xyz_access_point". Probably that is a better name for what I do here than xyz_config. xyz is the module being tested in this case, and this singleton class below is used to provide a means to use the static operator, ::, to access elements from anywhere in the testbench. ex: xyz_config::m_id_state.move_
  24. c4brian and I have messaged a bunch about ways to share data and access between elements in SV/UVM code. I put common functions/tasks/constants into a package, which I think is standard. I realize that absolute dot notation of accessing elements (i.e. variable12 = smthgA.smthgB.smthgC.variableXYZ;) is frowned upon as it is not good for reuse. So, the UVM presents the uvm_config_db to facilitate reuse and simplify connectivity across a hierarchy.**1 Many folks have (including c4brian, I believe) commented that they don't like how verbose it is to ::get from the config db
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