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ljepson74

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Posts posted by ljepson74

  1. Note/Clarification:
    With VCS 2019.06 and Riviera Pro 2020.04, the code in the original post works as I expected.

    cg_fa[0] - Coverage=78.12 %
    cg_fa[1] - Coverage=1.56 %

    I try to write code which has "universal" support across "all" simulators.
    Is the difference across simulators due to ambiguity in the LRM?  Is some aspect of my code using a poor style?  How can this code be improved for more universal simulator support?

    (I am trying to avoid publically contrasting simulators, which afaik is verboten.)

     

  2. Using an array of class objects which have a covergroup in them, I've run into the following problems.  I look for a solution which is supported by all/most simulators.  This topic array seems to be a common issue, based upon web search results.

    ERROR TYPE0: Same coverage is recorded for both covergroups, despite option.per_instance=1 being used.
    # vsim -voptargs=+acc=npr
    # cg_fa[0] - Coverage=81.25 %
    # cg_fa[1] - Coverage=81.25 %

    ERROR TYPE1: Compile error with another simulator
    cg_fa[0] - Coverage=xmsim: *N,COVNSM: (File: ./testbench.sv, Line: 42):(Time: 0 FS + 0) Sampling of covergroup type "cg_wrapper::cg" (./testbench.sv:7), referred in the statement is not enabled. As a result, coverage methods get_coverage(), get_inst_coverage(), get_hitcount(), and get_inst_hitcount() will return 0 coverage.

    Relevant LRM reference:  IEEE_Std1800-2017  19.8.1 Overriding the built-in sample method

    Code: https://edaplayground.com/x/6Zuh 

    Does anyone have a tip for either of these issues?

     

    package data_types_pkg;
    
      class cg_wrapper;
        covergroup cg with function sample ( bit [7:0] data );
          option.per_instance = 1;
    
          cp_data : coverpoint data[7:0];
        endgroup : cg
    
        function new();
          cg = new();
        endfunction
    
      endclass : cg_wrapper
    endpackage : data_types_pkg
    
    
    // MODULE: TOP
    //  The testbench of covergroup array
    module top;
      import data_types_pkg::*;
    
      cg_wrapper       cg_fa[2];
    
      initial begin
        $display("Make cg_fa[0]");
        cg_fa[0] = new(); //supply transaction as ref to covergroup instances instances
        cg_fa[0].cg.set_inst_name("cg_fa[0]");
    
        $display("Make cg_fa[1]");
        cg_fa[1] = new(); //supply transaction as ref to covergroup instances instances
        cg_fa[1].cg.set_inst_name("cg_fa[1]");
    
        //Sample each, but mainly [0]
        repeat (100) begin                       // many samples for [0]
          cg_fa[0].cg.sample( $urandom()%256 );  //  
          //#5;                                  // TRIED TO ADD DELAY SO DIFFERENT TIME SLOTS USED
        end                                      // ALSO TRIED TO CALL SAMPLE() from automatic function
        repeat ( 1)  begin                       // few samples for [1]
          cg_fa[1].cg.sample( $urandom()%256 );  // 
          //#5;
        end
    
        //Report coverage
        $display ("cg_fa[0] - Coverage=%0.2f %%", cg_fa[0].cg.get_inst_coverage());
        $display ("cg_fa[1] - Coverage=%0.2f %%", cg_fa[1].cg.get_inst_coverage());
      end
    endmodule

     

    As a side-note/question: If a simulator does not allow access to a covergroup's name with "cg.option.name" access (i.e. dot notation, such as to print it), then if name string is set with set_inst_name, how else can it be accessed?  Only in a tool output report?

  3. How can I write the following sequence?

    If sequence A happens, then sequence A may not happen again until either sequence B or sequence C happens.

    An example of the sequences might be:

    sequence seqA;
      ($rose(A)) ##1 $fell(A); //single cycle A pulse
    endsequence
    sequence seqB;
      B[->1];                  //B high for 1 cycle
    endsequence
    sequence seqC;
      (1[*10]);                //10 clk cylces
    endsequence

     
    It is important in this question that seqA is a sequence, so that we are not just checking 
    seqA |-> (!A throughout (seqB or seqC))
    (For this simple example, after seqA, perhaps a 2 cycle pulse of A is acceptable, before seqB or seqC.  So we specifically check for a 1 cycle pulse of A.)

    Although some auxiliary/extra code outside of the sequences and property (perhaps a small state machine) might help, I attempt to avoid extra code, to better understand SVA.

    One of my many failed attempts involves something like a liveness property.  Is this a correct/possible approach?

    sequence seqA_with_buffer;
      (##[0:$] seqA ##1 1[*]);
    endsequence
    seqA |-> ( (not seqA_with_buffer) ##0 seqB ##0 seqC )      
    
    //edit: Now that I look at this again (after posting), I don't think the buffer is needed ... if this could be made to work

    Some non-working code is here: https://edaplayground.com/x/5z5n 

  4. Thanks, David.
    Your response got me reading about the quality of RNGs (which was nice, but not my goal) and your initial example was in C.
    I was just looking for a way to make a simple system call (from SystemVerilog) to set the seed; to run a handful of times in succession with different seeds.

    I didn’t read far enough into Doug’s paper**1 to see his example code that you used in your most recent example.

    % head -4 /dev/urandom | od -N 4 -D -A n | awk '{print $1}'

    Your second example, www.edaplayground.com/x/Zve, is what I was looking for.  Thank you.  I use it as you suggested, and now can set the seed without needing to know the simulator options to use a random seed.

    **1 https://www.doulos.com/media/1293/snug2013_sv_random_stability_paper.pdf

  5. basarts,  Good point.   I had looked into “expr” and some other commands besides date, but should have been looking at exit codes.  (I must have been looking at various SV procedures that can be called as either tasks or functions, for too long.)  It seems any solution for my original question would require some external, non-SystemVerilog code and a DPI or similar call, which I’ll avoid for my current study purposes on edaplayground.  Thanks.

  6. Can a distribution value_range be a list? 
    Or is there way to achieve the same result using "dist"?

    As shown by non-working example code, I try to do something like this:

        bit [1:0] twobits;
        assert(std::randomize(twobits) with {twobits dist {2'b10:=50,  inside{2'b00,2'b11,2'b01;}:/50};} );   //INCORRECT
        assert(std::randomize(twobits) with {twobits dist {2'b10:=50,         [2'b00,2'b11,2'b01]:/50};} );   //INCORRECT

     "18.5.4 Distribution" image snippet from IEEE_Std1800-2017 LRM attached.

    Is there (isn't there) a way that value_range can be a list of choices, which are not in a range?  For example 00, 11, 01.
    I thought I had done this in the past, but now, a few years out of the SV game, I can't seem to get it to work.  I can think of other ways to 
    (Maybe an array holding the values, or something like that?  Perhaps I simply imagine that I ever did this using a dist.)

     

    LRM2017_Distribution.PNG

  7. Thanks a lot, David.
    My objective here is simply to be able to push "Run" on edaplayground a few times (usually <5), and to see different results.
    On Questa, I can use "-svseed=random".  I don't know the settings for all of the simulators, so tried an experiment to generate random seeds 100% from within SystemVerilog, as I wrote above (rather than using compiler/simulator switches).   For my purposes, if the randomess is not very good ... I don't care.  The quality of the randomness is not my objective here.  Thanks for that detailed reply, however.  You and Doug are great teachers.  I've been in very helpful Doulos classes with both of you.

    I'll minimize my questions to these:

    1) Can anyone get SystemVerilog's $system() function to return anything besides 0?  I have not been able to.  Is it not implemented or am I doing something incorrectly?
    2) What switches will provide random seeds for Aldec Riviera and Synopsys VCS?

     

     

  8. Does $system() really return an int when called as a function?  (Perhaps no one has implemented this part of the LRM?)

    int    myseed;
    myseed = $system("date"); //should output "return value of the call to system() with data type int"

    quote source: IEEE_Std1800-2017  Section 20.18.1 $system

    Quote

    $system makes a call to the C function system(). The C function executes the argument passed to it as if the argument was executed from the terminal. $system can be called as either a task or a function. When called as a function, it returns the return value of the call to system() with data type int.

    I have not been able to get a non-0 return value, as far as I can tell.  Am I doing something incorretly or is this not implemented? 

    What if $system("date") is called?   I suppose the "date" system output is longer than 32b, so perhaps the lowest bits are all 0s and the upper ones that contain the date are truncated.  ?

    Some sample code: https://edaplayground.com/x/4dw6 

    ====================================================================

    Ultimate Objective: Use $system("date") to set the seed using $srandom().
    Reason: I haven't easily found the simulator run switches for the different simulators to use random seeds for each run.  So, I try to make universal SystemVerilog code (just for use on edaplayground with small examples), to use a random seed for each run, based on the wall clock time.
     

    //Compiler / simulator run switches to set random seed in SystemVerilog simulators
    Aldec Riviera:    ? ? ?
    Cadence Xcelium:  -seed random
    Mentor Questa:    -svseed=random
    Synopsys VCS:     ? ? ?

    (I feel comfortable posting this, as I don't consider this any form of benchmarking between simulators, but just equating compile options.)

  9. @kurtlin , do you know this by chance?   

    I am looking for each VCS simulation 'run' to use a different seed. 

    (I'm using EDAPlayground, so don't have access to a set of user guides.)

     

    On a related note to compile switches, besides replacing -sverilog with -sv=2009, as you showed in another thread **1, I found this below.  (I suspect that -sv=2009 is a superset of "-assert svaext".  So, I'll probably stick with that.  Thanks again.)

    Quote

    "You must use the –assert svaext compile-time option to enable the new IEEE Std. 1800-2009 compliant SVA features."

     

    Perhaps I might set the seed from within the code, performing a string operation on the output of $system("date")

    **1: 

     

  10. Thank you.  I could not (easily, so I gave up) find information about the compiler switches online. 

    a) -sv=2009 works and the compiler error disappears

    b) The assertion AS_TRUE5_STRONG does not fail, as expected, based on the LRM description of "strong".

    IEEE_Std1800-2017 : 16.12.2 Sequence property

    Quote

    strong(sequence_expr) evaluates to true if, and only if, there is a nonempty match of the sequence_expr.

    Aren't the clock cycles of the sequence which do not complete (because the simulation ends) empty matches?

     

  11. The below assertions check that gnt is not high for consecutive clk cycles.

     Q1: v1 vs. v2: Are there benefits or relevant differences between these styles.
     Q2: v2 vs. v3: Does the placement of delay matter?
    Besides for end of simulation termination.

     The questions are mainly about whether some style is better for the simulator, or there is some non-obvious situation I should consider.
     

    module top;
      bit clk, gnt;
      bit [19:0] gnt_a;
    
      initial begin
        gnt_a = 20'b0011001010_0000001101;
        #200 $finish;
      end
    
      assign gnt = gnt_a[19];
    
      always clk = #5 ~clk; 
    
      always@(posedge clk) begin
        gnt_a = gnt_a<<1;
        $display($time," gnt: %1b",gnt);
      end
    
      as_v1 : assert property ( @(posedge clk)
                               not strong(gnt[*2])
                              );
        
      as_v2 : assert property ( @(posedge clk)
                               gnt |-> ##1 !gnt
                              );
          
      as_v3 : assert property ( @(posedge clk)
                               gnt ##1 1'b1 |-> !gnt
                              );
    endmodule

     

    Code is also available here: https://edaplayground.com/x/4GXn 

  12. Does VCS 2019.06 support strong and weak?   (Or is there a VCS switch needed to use LRM 2009+?)
    I get the following error with the code below.

    Error-[IND] Identifier not declared
    testbench.sv, 15
      Identifier 'weak' has not been declared yet. If this error is not expected, 
      please check if you have set `default_nettype to none.
      
    
    
    Error-[IND] Identifier not declared
    testbench.sv, 16
      Identifier 'strong' has not been declared yet. If this error is not 
      expected, please check if you have set `default_nettype to none.

     

    Code:

    //Weak & Strong seem to not work in VCS 2019.06
    module top;
      bit clk;
    
      initial begin
        #100;
        $finish;
      end
    
      always
        clk=#5~clk;
    
      AS_TRUE5        : assert property (@(posedge clk)        (1[*5]) ); //per 2009+ LRM, this should be weak by default, so pass
      AS_TRUE5_WEAK   : assert property (@(posedge clk) weak   (1[*5]) ); //per 2009+ LRM, this should pass
      AS_TRUE5_STRONG : assert property (@(posedge clk) strong (1[*5]) ); //per 2009+ LRM, this should fail **1
    
          //**1:  Should fail because at end of sim, there will be one or more start cycles, which were not the start of five cycles (because sim ends).  So for those, the seq does not complete
    endmodule

     

    https://edaplayground.com/x/29PM
     

  13. mastrick,

     Thanks for that.   That is a very good point. 
      For forums or any sort of Q&A I try to show the focus of the post as succinctly as possible.  Doing so, I sometimes use styles I wouldn't ordinarily, like skipping a "begin ... end" when it is not required because there is only one line of code.  (I like to always use begin/end and heavily use parentheses to be explicit.)
     I agree with your point.

     

    Why am I responding to threads from 4 years ago, one might ask?   Because after 3 years of not using UVM and almost no SystemVerilog, I am trying to get the rust off by revisiting questions I've had in the past.  Yes, I was working at a place that favored vanilla Verilog, and where SystemVerilog was discouraged and UVM was not used.

  14. Note: There will be a reply coming soon by user “jdickol”.  (He recently registered, so his reply likely needs moderator approval, but he messaged me directly.)   Thanks for the solution, jdickol.
     

    This is how the constraint can be written:

       constraint total_weight {
          (animal_da.sum with (item.weight)) == 100;
        }


    Output:

    # animal weight:39
    # animal weight:24
    # animal weight:37
    # ***********************Total weight: 100
    # animal weight: 7
    # animal weight:36
    # animal weight:57
    # ***********************Total weight: 100
    # animal weight:48
    # animal weight:28
    # animal weight:24
    # ***********************Total weight: 100

     

    And because I often refer to old questions I've asked on this forum, I'll post the follow-up question and answer here.
    Q: Can the constraint dive further down through class handles?  
    A: Yes.   In example below and attached "parasite_m" is a class handle.

    animal_da[jjj].weight > animal_da[jjj].parasite_m.weight;

     

    accellera_forum_sv_constraint_animals_parasites_question.txt

  15. I've simplified the example.

    Goal: Using constraints in group_of_animals_c, can we constrain the sum of the animal weights?
    I'd prefer to avoid procedural code in functions being called.  My goal is understand if/how a constraint might reach thru class handles and affect properties in the objects contained by the object which is being randomized.

     

    //Class animal_c has a property "weight".
    //For an array of animal_c (as part of class group_of_animals_c),
    // the total weight of the animals should be 100.
    //How can this be done with constraints?
    //Can a constraint expression reference properties referenced by handles?
    //
    //My goal is to better understand contraints, so I attempt to stuff as much
    // as possible into the constraints of class group_of_animals_c.
    
    module top;
    
      class animal_c;
        rand int   weight;
        constraint weight_legal_c {weight>1; weight<60;}  //allowed weight per animal.
    
        function void show();
          $display("animal weight:%2d", weight);
        endfunction
      endclass
    
    
      class group_of_animals_c;
        rand animal_c  animal_da[3];
    
        function new();
          foreach (animal_da[jjj])
            animal_da[jjj]=new();
        endfunction
    
        function void post_randomize();
          int sum_weights=0;
          foreach(animal_da[iii]) begin
            animal_da[iii].show();
            sum_weights+=animal_da[iii].weight;
          end
          $display("***********************Total weight: %0d",sum_weights);
        endfunction
      endclass
    
    
      initial begin
        group_of_animals_c  group_m;
        group_m             = new();
        repeat (3) assert(group_m.randomize());
      end
    
    endmodule

    https://www.edaplayground.com/x/2NZE

  16. Thanks, David.  Instead of using post_randomize(), I moved some of the work to pre_randomize().  That helped.   I show the code below.  But to get to the heart of the question I have, I will try to further shrink the code in a subsequent post.

    //Class animal_c has a property "weight".
    //A dynamic array is generated where each element points to an animal.
    //The cumulative weight of the animals should be 100.
    //How can this be done with constraints?
    //Can a constraint expression reference properties referenced by handles?
    //
    //My goal is to better understand contraints, so I attempt to stuff as much as possible into the constraints.
    
    module top;
    
      class animal_c;
        rand int   weight;
        constraint weight_legal_c {weight>1; weight<40;}  //allowed weight per animal.
    
        function void show();
          $display("animal weight:%2d", weight);
        endfunction
      endclass
    
      class group_of_animals_c;
        int initialized;
        int num_animals;
        rand animal_c  animal_da[];
    
        function void pre_randomize();
          if (!initialized) begin
            assert( std::randomize(num_animals) with { num_animals inside {[3:12]}; } );
            animal_da = new[num_animals];
            foreach (animal_da[jjj]) begin
              animal_da[jjj]=new();
            end
            initialized=1;
          end
        endfunction
    
        function void show_group();
          foreach(animal_da[iii])
            animal_da[iii].show();
        endfunction
      endclass
    
    
      initial begin
        group_of_animals_c  group_m;
        group_m             = new();
        assert(group_m.randomize());
        group_m.show_group();
      end
    endmodule

     

  17. Can a single constraint be used across an array of objects?   i.e. affecting the relation between a property which exists in each of those objects?

    I'm trying to do something like an array reduction or sum, but instead of performing it on an array, performing it on the properties of objects in an array.
    My goal is to better understand the capabilities of constraints.

    Example below: (I do not show my failed attempts.)

    //Class animal_c has a property "weight".
    //A dynamic array is generated where each element points to an animal.
    //The cumulative weight of the animals should be 100.
    //How can this be done with constraints?
    //Can a constraint expression reference properties referenced by handles?
    //
    //My goal is to better understand contraints, so I attempt to stuff as much as possible into the constraints.
    
    module top;
    
      class animal_c;
        rand int   weight;
        constraint weight_legal_c {weight>1; weight<40;}  //allowed weight per animal.
    
        function void show();
          $display("animal weight:%2d", weight);
        endfunction
      endclass
    
    
    
      class group_of_animals_c;
        rand animal_c  animal_da[];
    
        constraint number_of_animals_c { animal_da.size() inside {[3:5]}; }
    
        //As I understand, array objects cannot be constructed in the randomize call that determines the array size.  (T or F?)
        //so, post_randomize seems the natural place to construct the objects in the array.
        function void post_randomize();
          foreach(animal_da[iii]) begin
            animal_da[iii]=new();               //create each object of array
            assert(animal_da[iii].randomize());
          end
        endfunction
        
        function void show_group();
          foreach(animal_da[iii])
            animal_da[iii].show();
        endfunction
      endclass
    
    
      initial begin
        group_of_animals_c  group_m;
        group_m             = new();
        assert(group_m.randomize());
        group_m.show_group();
      end
    
    endmodule

    https://www.edaplayground.com/x/4Dx5 

  18. @uwes, thank you.  For better or worse, the project that I work on for this does not use UVM.  (Yes, I realize that this is a UVM forum and that my question is just a vanilla SV one.)   I'll keep this response you sent in mind for the future and look forward to trying it.  That looks like a clear and terse solution - which is what I look for.  (Hopefully my next project uses UVM.)

    @chr_sue, Thanks.  But what I try to do is the reverse.  i.e. to see if the value of my_string (which is of type string) is one of the my_enum states.   So, using the cast style you show, I'd need to cast each state of my_enum to string, and then compare it.  As it is, I can just do a direct compare to see if there is a match, without any cast.   Thank you, though.  You got me thinking about this differently.

    For now, I just walk thru my_enum and check each state for a match with my_string, to see if my_string has a legal value.

    (To provide some more details, I am checking that a command-line input plusarg string is of a legal value for the test.  The legal values are stored as an enum.  Storing them as an enum allows them to be used elsewhere; as opposed to just having an array of legal string values.)

  19. Is there an easy (concise, maybe one-liner) way to check if a string is 'inside' an enum?

    i.e.   

    typedef enum {alpha, beta, gamma, delta, epsilon} my_enum;
    string my_string;
    my_string = <something>; 
    
    //I know this is not possible, but I try to do something like this
    if (my_string inside {my_enum.names})  // where names would imply all of the enumeration option strings

     

    I try to avoid walking thru all of the enumerated values, which is what I currently do (and which works fine).

  20. *,

    How can I randomize with a dist and specify a weight for values not being inside a range?

     class randclass;
        rand logic [3:0] randvalue;
    
        function void post_randomize();
          $display("value: %0d",randvalue);
        endfunction
    
       constraint inside_practice {
         randvalue dist {
           [3:4] :/ 50,
           !(inside {[3:4]}) :/ 50    //<---  I try to have a sort of 'others' category here
         };
       }   
     endclass
    
    module top;
      randclass randclass;
    
      initial begin
        randclass = new();
        repeat (10) begin 
          randclass.randomize();
        end
        $finish();
      end
    endmodule

     

    Reference:  https://www.edaplayground.com/x/cV5 

     

    shaking off the rust after a SystemVerilog hiatus,

    thanks

     

  21. I recently encountered SVA code which results in different results on different simulators.  I've shrunk it to a simple example here.

    I believe this code should cause an error, but it does not on all tools.   Can someone comment on how the 2017 LRM should be interpreted (and perhaps on the code).
    (I sense someone will comment on the driving signals in the code.)

     

    module top;
       bit   clk;
       logic sig1;
       logic disable_assert;
    
       always begin
          #5 clk=0;
          #5 clk=1;
       end
     
       initial begin
         disable_assert=1'b1;
         sig1          =1'b0;
         $display("Hello World");
         $monitor($time," **** sig1:%0b  disable_assert:%0b",sig1, disable_assert);
         repeat (3) @(posedge clk);
         @(posedge clk); sig1=0; disable_assert=1;
         @(posedge clk); sig1=1; disable_assert=1;  //2a. assertion would fail, but it is disabled
         @(posedge clk); sig1=0; disable_assert=0;  //2b. now assertion is enabled and should fail** 
         @(posedge clk); sig1=0; disable_assert=1;
         #20;
         $finish();
       end
    
       property as_disable_testing;
          @(posedge clk) disable iff (disable_assert)
         !sig1;
       endproperty
    
       assert property (as_disable_testing);
    endmodule : top

     

    Question: Should there be a timing error at comment 2b, or not?

     

    Code is here to play around with: https://www.edaplayground.com/x/njR 
    Picture: https://docs.google.com/drawings/d/1qQB4dB5w8_1jx73xta46RbmLzkparaNcxHNdLgi8YNY/edit?usp=sharing 

     

    These are my thoughts:
    // It seems this small code snippet should cause an error, but tool results differ.
    //
    //
    // NOTE: Yes, I realize that I am using tools from BEFORE 2017, but comparing results to the 2017 LRM.
    // What is the correct LRM interpretation?  What comments do gurus have about this code?
    //
    //
    //1) Run the code with Aldec Riviera Pro 2015.06, Synopsys VCS 2014.10, and with Cadence Incisive 15.20.
    //   RIVIERA PRO and IRUN show assertion failures.
    //     VCS does not show assertion failure.
    //     
    //2a) This is time when sig1=1 assertion 'would' fail, but it is disabled (disable_assert==1)
    //2b) **On next clock cycle the assertion set to be enabled (i.e. disable_assert==0).
    //    The SystemVerilog 2017 LRM (1800.1-2017.pdf) describes the behaviour.
    //    At the start of the 2b time slot (see page 64 of SystemVerilog LRM 1800.1-2017),
    //      PREPONED REGION: the values of the assertion are sampled (sig1==1)
    //      ACTIVE/INACTIVE/NBA regions: the values are updated (sig1,disable_assert)
    //                                   (so you can use either blocking "="
    //                                    or you can use non-blocking "<="
    //                                    and you will get the same result)
    //                                    So for this time slot: sig1==0, disable_assert=0
    //      OBSERVED REGION: this is where the assertion is evaluated, using values sampled from 
    //                                    the preponed region (so sig1==1).
    //                                    However, the value of disable_assert is not from the 
    //                                    preponed region, but simply whatever the value is, 
    //                                    as assigned in the active/inactive/nba region. 
    //
    //
    // Section 16.6 of the SystemVerilog LRM (1800.1-2017 states: "The expressions in a disable condition are evaluated using the current values of variables (not sampled) ..."  I believe this means from whatever is set in the Active/NBA region of current time slot.
    // 
    // Section 16.12 of the same document states: "If the disable condition is true at anytime between the start of the attempt in the Observed region, inclusive, and the end of the evaluation attempt, inclusive, then the overall //evaluation of the property results in disabled."
    //
    // My conclusion: The sig1 value from 2a will be used in 2b when disable_assert=0;  ***Assertion should fail.***
    //
    // Picture: https://docs.google.com/drawings/d/1qQB4dB5w8_1jx73xta46RbmLzkparaNcxHNdLgi8YNY/edit?usp=sharing
     

     

     

     

     

     

  22. What is the proper forum to request that this be more clear in the next LRM release?  Should I send that request to the IEEE now, instead of Accellera?

    Request: 
    1) "time step" vs "step time" - Use only one or the other (or state their equivalence, to help people who search the doc for the term).
    2) Describe relationship between "time step unit" and "time slot".
     

  23. Both the 2005 and 2017 LRMs contain this statement:

    Quote

    "The step time unit is equal to the global time precision."

    The 2017 LRM also states:

    Quote

    "The global time precision, also called the simulation time unit, is the minimum of all the timeprecision
    statements, all the time precision arguments to timeunit declarations, and the smallest time precision
    argument of all the `timescale compiler directives in the design."

     

    So, in searching for the definition of "time step", as used in the 2017 LRM, I should have been searching for just "step".

    In response to my question above, I offer the following definition of the relationship between "time slot" and "time step".

    A "time step" is the distance between two adjacent "time slot"s, or is simply used to refer to a successive "time slot".   i.e. When you advance a "time step", you simply move to the next time slot.

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