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  1. Like
    uwes got a reaction from ljepson74 in uvm_builtin_reg_test_seq & default sequences   
    this sounds like a bug. normally the sequence and/or items do know on which sequencer they run on *or should run on". there are a few situations where that in of is/was missing. a recent issue i remember was one where when an item was sent to a low level bfm sequencer from a virtual sequence running on a null sequencer then the sequencer info was wrong leading to similar fails..
  2. Like
    uwes got a reaction from ljepson74 in Check if string is 'inside' an enum   
    have a look at uvm_enum_wrapper in uvm12+. you could simply do the following (untested)
    class myenumwrapper#(type T) extends uvm_enum_wrapper#(T); static function bit is_inside(string x); return map.exists(x); endfunction endclass // and later myenumwrapper#(my_enum)::is_inside("alpha")   
  3. Thanks
    uwes got a reaction from u24c02 in Unrecognized system task or function: $cdn_ahb_access   
    the technical part of the error is that you missed to include the system functions into your command invication (something like -loadvpi, -svlib or similar). nevertheless i would recommend the file a support ticket to have this resolved.
  4. Like
    uwes got a reaction from jcvobu in How to get the value of a string when using the string in a hierarchical path   
    uvm gives you the ability (via vpi) to write using ```uvm_hdl_deposit(string path, value)```
  5. Like
    uwes got a reaction from ljepson74 in When a phase completes, are any lingering processes terminated?   
    the answer is "it depends".
    - threads started inside or as a child-thread of  xyz_phase() are terminated before phase progression
    - threads started inside phase_started() are NOT terminated automatically and continue to run until normal end or explicit termination.
  6. Like
    uwes got a reaction from karandeep963 in uvm reg limitation   
    there should be no limitations affecting you. there might be simulator limitations (size of arrays etc.) but even those are far away. the typical bounds for the register model are defined by the number of types (registers, registerfiles,...) and instances for compile/elab/simulation. these are soft (=handling) bounds (memory+time) rather then implementation bounds.
  7. Like
    uwes got a reaction from karandeep963 in how do we sort the UVM_REG space based on address?   
    the access should go through the map for which you have extracted the addresses. Instead of 
    sorted_regs_ntb.next[idx].write(status, wdata, parent(this); it should be
    foreach(sorted_regs_ntb[idx]) sorted_regs_ntb[idx].write(status, wdata, parent(this),map(map));
  8. Like
    uwes got a reaction from tudor.timi in FATAL UVMREG register write operation   
    if im not mistaken the tool should have rejected this assignment since its not type compatible in the first place.
       extern virtual function void set_sequencer (uvm_sequencer_base sequencer, uvm_reg_adapter    adapter=null);
      both should have the same effect. when you distribute the same regmodel to different sequencers then the wildcard is usually better (simpler+faster).     
    i usually prefer the ::get(get_sequencer(),"","reg_model", model)
    because it avoid the string handling, is to some extend type safe and it doesnt use the m_* variable (which is an uvm internal). Also it might be better to further expand the check. 
        if(!(uvm_config_db#(dutblk)::get(get_sequencer(),"","reg_model", model))) begin
          if(model==null) `uvm_fatal("NO_REG_CONFIG","reg model set to NULL") 
        end else
          `uvm_fatal("NO_REG_CONFIG", "Seq reg model was not set"
  9. Like
    uwes got a reaction from karandeep963 in who can interpret use of soft constraint ?   
    asking for help but raise the question in some other forum isnt helpful.
  10. Like
    uwes got a reaction from tudor.timi in who can interpret use of soft constraint ?   
    asking for help but raise the question in some other forum isnt helpful.
  11. Like
    uwes got a reaction from Parth in Multithread and automatic variable   
    what you essentially wrote in case#2 is 
    module my_module;      int a=0;      initial      begin        for(int i=0;i<5;i++)        begin               fork                  // Check differance here , between 2 statements                  // ##case 1 (declaration and assignment). automatic int j= i;                 // and                  automatic int j;  // ##case 2 declare  begin                 j=i;                  //  then assign end                 begin                     $display("Chk auto %d",j);                 end              join_none         end     end  endmodule : my_module note that the $display and the "j=i" are actually parallel threads (a race). if you switch the order of the two  blocks your result might be different (if your simulator chooses this)
                    begin                     $display("Chk auto %d",j);               end     begin                 j=i;                  //  then assign end   so for what you want to accomplish case#1 is the right path.   /uwe
  12. Like
    uwes got a reaction from amitk3553 in Polymorphism in testbench   
    polymorphism is a general concept. see http://en.wikipedia.org/wiki/Polymorphism_(computer_science). the testbenches we write are essentially software. in that sense all methods to improve creation/speed/maintenance/stability/reuse of software should be in the focus for tb developers too. the concept of polymorphism is one way to improve.
  13. Like
    uwes got a reaction from David Black in Compilation error in IUS9.2-S023   
    do yourself a favor and upgrade to a recent version of ius such as 12.20,13.10,13.20. ius9.2 is out of maintenance for 3years and i do not remember the qualified uvm versions there. in addition using the latest uvm11d will also prevent quite some error seen in earlier versions.
  14. Like
    uwes got a reaction from getvictor in How to call uvm_error from a static method?   
    in static contexts you have to use the macro set with the postfix "_context". while the normal macros will invoke <this>.uvm_report_xyz() and therefore require a non static context the _context macros will invoke <context>.uvm_report_xyz(). messages emitted with the _context version can be used in static contexts and provide the same functionality as-if the non-context version would have been invoked in context.
    (an alternate use model for the _context macro version is to emit a message from a different place than what appears as the messages context. eg. you can print from within the driver BUT the context is showing as if the message was emitted by the agent)
  15. Like
    uwes got a reaction from cliffc in `uvm_info_context - why use it?   
    the *_context variant of the macros can be used when you want the message to appear as if emitted by another object. a common use model would be if all your components use a common helper class which emits a message then typically you want instead of your common helper class appearing in the message the parent component to be printed. 
    the _context macros are just
    `define uvm_*_context(ID, MSG, CNTXT) \    begin \      if (CNTXT.uvm_report_enabled(...)) \        CNTXT.uvm_report_* (...); \    end    
  16. Like
    uwes got a reaction from Rakesh in Having Power Aware and Performance verification component integrated   
    here is some info howto do that
  17. Like
    uwes got a reaction from ggupta in How to pass register model for in-built sequence??   
    you need to set some_uvm_reg_hw_reset_seq_instance.model to your register model
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