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Michael Privett

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  1. Based on my testing, an additional change will be required in the class uvm_reg_bit_bash_seq.svh. My assumption here is that the fix for this issue is adding the "begin" at line 1404 (above) and "end" at (1419). Problem 1: uvm-1800.2-2020.1 uvm_reg_bit_bash_seq.svh contains the following line to calculate the expect value: exp = rg.get() & ~dc_mask; // from line 173 With the planned fix, the mirror and desired values remain the same. The problem is that when the desired value is non-zero, a non zero value is expected in the later comparison, which will result in a miscompare. if (val !== exp) begin // Line 181 Potential Fix: change to exp = rg.get_mirrored_value() & ~dc_mask; // from line 173 Problem 2: The bit bash status comparison should be configurable Here's the code in question: 175 if (status != UVM_IS_OK) begin 176 `uvm_error("uvm_reg_bit_bash_seq", $sformatf("Status was %s when reading register \"%s\" through map \"%s\".", 177 status.name(), rg.get_full_name(), map.get_full_name())) 178 end An error status may be correct and required by the architecture. For example, an APB slave may be required to assert slave error for an illegal write. For this case, we should be able to disable this error in the sequence (perhaps config_db set). In our TBs, we don't need the register tests to "check" the bus error status (status), we let our scoreboard handle that. Thoughts?
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