I have a question similar to https://forums.accellera.org/topic/2126-genericruntime-specification-of-ports/
I want to sweep through a set of wordlengths in a design space exploration task, i.e. test whether the system (including functional behaviour of the algorithm) works with signals of type sc_fix with e.g. 3 integer + 3 fractional bits, 2+4 or 4+2. All with the same build target (i.e. without re-compiling every time), i.e. the word lengths of the signals and corresponding module ports should be read from a file and then be used in the constructors (of the signals, and module-ports) at run-time.
However, I did not succeed. My approach was to pass the wordlengths of the sc_fix to the constructor of sc_signal (or the port), but there is apparently no sc_signal, sc_in, … constructor that accepts this additional input.
My next approach was, that the sc_signal<sc_fix> can apparently be configured by the current context parameters, when it is constructed. When I have ports in a module, however, they are constructed “en bloc” (during module construction) and I cannot set the context for each port individually. So this approach does not work either.
Do you maybe have an idea how to solve the problem?
Many thanks in advance,