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Everything posted by Ming

  1. Yes, member function initialize() works. SC_CTOR(uart): int_o("int_o") { int_o.initialize(0); ... Thanks. Regards, Ming
  2. Oh Thanks. I found my issue. I initialized the sc_out port in the constructor of module A. SC_CTOR(uart): int_o("int_o") { int_o = 0; ... After removing that line, the model run successfully. I notice while we initialize sc_out in SC_CTOR, the sc_out port is actually not bound. So we can't initialize port in constructor. Thanks again. Regards, Ming
  3. Thanks for your quick response. Related code is attached below. Could you please help take a look? (I'm building a simple SoC, all codes will be messy, so just list related codes here) module A: struct uart: sc_module { sc_out<sc_int<1> > int_o; ... module B: SC_MODULE(tb) { sc_out<sc_int<6> > int_o; sc_in<sc_int<1> > int_timer_i; sc_in<sc_int<1> > int_uart_i; void gen() { int_o.write(((int_timer_i.read()) & 0x1) | ((int_uart_i.read() & 0x1)<<1)); } SC_CTOR(tb) { SC_METHOD(gen) sensitive << int_timer_i << int_uart_i; dont_initialize(); } }; sc_main: int sc_main(int argc, char ** argv) { sc_signal<sc_int<6> > int_vector; sc_signal<sc_int<1> > int_timer; sc_signal<sc_int<1> > int_uart; sc_signal<sc_int<1> > int_uart_pc; uart * target1_uart; tb * testbench; target1_uart = new uart ("Target1"); testbench = new tb ("testbench"); target1_uart->int_o(int_uart); testbench->int_o(int_vector); testbench->int_timer_i(int_timer); testbench->int_uart_i(int_uart); Regards, Ming
  4. I have a port defined as 'sc_out<sc_int<1> > outa' in module A, a port defined as 'sc_in<sc_int<1> > inb' in module B, then a channel defined as 'sc_signal<sc_int<1> > sig' in sc_main, then in sc_main 'A.outa(sig); B.inb(sig);'. Then I got an error message attached below. Error: (E112) get interface failed: port is not bound: port 'Target1.int_o' (sc_out) In file: ../../../src/sysc/communication/sc_port.cpp:235 Could you please help? Thanks.
  5. Got it. Thanks. I'm looking at an example, port-to-port really happened for hierarchical connection, and I missed channel definition parts. Thanks again.
  6. There is sc_in A in module MA, sc_out B in module MB. MA.A is binded to MB.B directly. Can we assign value to B in MB? But where is the channel? As I know, sc_in and sc_out are all sc_port with related interface, we should have related channel to be connected to these two ports. Thanks in advance.
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