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qurax

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  1. Hi all, I got a question regarding RAL. Assuming there are 2 registers A and B whose width are 8 bits and 16 bits respectively and the bus width is 8 as well. The two UVM registers are created by new(name, 8, UVM_NO_COVERAGE) and new(name, 16, UVM_NO_COVERAGE) for defining their own width. Register A and B locate at address 0 and 1-2 as the address is byte aligned. An user defined register map is created uvm_reg_map my_map = create_map("my_map", 0, 1, UVM_LITTLE_ENDIAN, 1); my_map.add_reg(reg_A, 0, "RW"); my_map.add_reg(reg_B, 1, "RW"); After reg_B.write(status, 16'habcd, .path(UVM_FRONTDOOR)), I would expect 2 transactions with 8 bits each appearing on the bus. However, there is only one access of h'cd to address 1. The other one never comes and it ends up throwing an error "There are 1 incomplete register transactions still pending completion" which is caused by a check on outstanding register accesses pending in predictor in check phase. I tried to find out how the original data value in uvm_reg_item gets split in reg2bus() function. It seems correct that the original data in uvm_reg_item is h'abcd and split to h'cd in uvm_reg_bus_op. But again the other part of data does not come. Also tried to search for answer from other places, for instance the same issue here https://verificationacademy.com/forums/uvm/how-handle-registers-are-wider-bus, it didn't help much unfortunately. If you have any clue about this, please leave your comments. Thanks.
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