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zidane

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  1. Thanks @maehne, I think I understand the issue now. If I expect the algorithm to run in pipeline, and II = 1. I think I can add the setting in tool like Stratus, but how to achieve same thing just in simulation. (currently, I'm using Eclipse) Update: I tried to use wait() in the loop. Seems working as I will be updated at each clock cycle. Will this method impact with Stratus scheduling and optimization?
  2. Hi @maehne and @AmeyaVS Thanks for the follow up. Here is the code snippet regarding with IO. I also attached full code as well.
  3. Hi @AmeyaVS I didn't paste all code (like IO and SC_THREAD) here otherwise it may become a length thread. But I think the code is structurally OK or the systemc simulation wont run. More about SC_THREAD This mac class will be called from sym_hbf_2x class. And the latter be called from tx_fir_0_1_4 which is called in tx_top cthread process().
  4. Hi @AmeyaVS Thanks for the response. I have update the post including more info you ask. Thanks Zidane
  5. I'm learning systemc at early stage, so pls forgive me if it's a stupid question. Code below is a fixed-point mac for FIR. This mac class will be called from sym_hbf_2x class. And the latter be called from tx_fir_0_1_4 which is called in tx_top cthread process(). When I dump the values into VCD, the index "i" stucks at "4". But other internal signals (like *_out) shows the for loop is running. How can I dump the accurate internal signals states into VCD? template<int in_bw, int out_bw, int tap, int coeff_bw, int mul_trunc, int acc_trunc> class sym_fir_mac{ public: static const int mul_bw = in_bw + coeff_bw - mul_trunc; static const int acc_bw = mul_bw + acc_trunc; //This line doesn't work //Cannot cast double to const int? // const int acc_trunc = ceil(log2(tap)); sc_uint<3> i; sc_int<in_bw+1> data; sc_fixed<mul_bw, mul_bw, SC_TRN, SC_SAT> mul_out; sc_fixed<acc_bw, acc_bw, SC_TRN, SC_SAT> acc_out; sc_int<out_bw> mac_out; sc_int<TX_BITS> inst(sc_int<in_bw> *reg, sc_int<coeff_bw> *coeff) { for(i = 0; i<tap; i++) { data = reg[i] + reg[2*tap-1-i]; mul_out = ((data * coeff[i]) >> mul_trunc); acc_out = acc_out + mul_out; } mac_out = (acc_out >> acc_trunc); return mac_out; } }; template<int in_bw, int out_bw, int tap, int coeff_bw, int mul_trunc, int acc_trunc> class sym_hbf_2x { public: sc_bit state; sc_int<TX_BITS> latched_data_out; sym_fir_mac<16,16,tap,coeff_bw,mul_trunc, acc_trunc> mac; sc_logic busy_out; sc_int<TX_BITS> data_out; void reset() { state = 0; data_out = 0; latched_data_out = 0; busy_out = 0; } sc_int<TX_BITS> inst(sc_int<16> *data_in, sc_int<coeff_bw> *coef, sc_logic busy_in) { if (busy_in == 0) { switch(state) { case 0 : data_out = mac.inst(data_in, coef); case 1 : data_out = data_in[2*tap]; } latched_data_out = data_out; } else { data_out = latched_data_out; // restore the data busy_out = 1; } return data_out; } }; class tx_fir_0_1_4 { public: sym_hbf_2x<16,16,4,20,13,2> fir0; sc_int<16> fir0_data_in[8]; sc_int<16> fir0_data_out; sc_logic fir0_busy_out; public: void reset() { cout << "tx top:" << "start reset tx_top" <<endl; fir0.reset(); fir0_coeff[0] = -234; fir0_coeff[1] = 1320; fir0_coeff[2] = -4706; fir0_coeff[3] = 199997; } sc_int<TX_BITS> inst(sc_int<16> *data_in, sc_logic busy_in) { cout << "tx top:" << "start inst tx_top" <<endl; if(fir0.busy_out == 0) { for (int i=7; i>0; i--) { fir0_data_in[i] = fir0_data_in[i-1]; } fir0_data_in[0] = *data_in; } fir0_data_out = fir0.inst(fir0_data_in, fir0_coeff, busy_in); return fir0_data_out; } };
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