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Xing Chen

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  1. Eh, if this is inside a larger heirachy/clk tree, I think it's hard to get it work alongside the other branches. Thanks for the idea though! Is it possible avoid the clock switch to become a separate delta cycle?
  2. Hello, I'm trying to simulate a sync clock gater in SystemC: input: clk, clk_enable, output: enabled_clk. However, I noticed that having a SC_METHOD over clk breaks the sync design: #include "systemc.h" SC_MODULE(ClockPropagater) { sc_in<bool> clk{"clk"}; sc_out<bool> p_clk{"p_clk"}; // Clock gating can be potentially added. void Propagate() { p_clk = clk; } SC_CTOR(ClockPropagater) { SC_METHOD(Propagate); sensitive << clk; }
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