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OMark

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  1. @David Black As proposed, here is an illustration of what I try to achieve. In the original design, I have SystemC modules "A" and "C" connected directly, where the sc_port of the module "C" uses the Interface provided by sc_export of module "A". Now, I added a module "B" which is supposed to route flexibly the signals and forward their values to destination. I succeeded to achieve the binding between modules "A", "B" and "C" as illustrated in the picture. But I am not sure how to forward efficiently the values from the sc_port of the "B" module to the sc_export of that same module to be consumed by the Module "C" as done originally. Is the sketch clear?
  2. Hello, I have a systemC module having an input sc_in<bool> and an output sc_export<sc_core::sc_signal_inout_if<bool>>. How can I route the signal values coming on the input systemc port to the export port? Is that even doable and under which conditions? Thanks.
  3. Hello, I tried out your method as follows: sc_object* test_object_find = sc_core::sc_find_object(port_name); sc_core::sc_object& obj = dynamic_cast <sc_core::sc_object&>(*test_object_find); PortElement<sc_logic>* PE = new PortElement<sc_logic>(count,hierarchical_name,port_name,obj); sc_core::sc_attribute<PortElement<sc_logic>*> attr{"PortElement", nullptr}; attr.value = PE; Until here, I am capable to build and run without issue. Then when I follow up the above lines of code with this one: obj.add_attribute(attr); I can build, but when I run the simulation it crashes suddenly. Which failure did I make when adding the attribute to the port object? Thanks for your help.
  4. Hello, I have defined one class "Class A" and when creating instances of that class e.g. A* instA1 = new A (); I want to attach the instA1 object to an sc_in port of my SystemC module as an attribute of that port. - Can I use for that purpose the add_attribute function? - How safe is that? - Are there any other recommended mechanisms (as alternatives)? Thanks.
  5. Hello, Thanks @Eyck for your prompt response. I corrected the code example as below and the binding works fine now. #include "stdafx.h" #include "systemc.h" struct test_producer : sc_module{ sc_out<sc_dt::sc_logic> out1; sc_out<sc_dt::sc_logic> out2; SC_HAS_PROCESS(test_producer); test_producer(::sc_core::sc_module_name){ SC_THREAD(test_prod); } void test_prod(){ while (1){ out1.write(SC_LOGIC_0); out2.write(SC_LOGIC_0); wait(10, SC_NS); out1.write(SC_LOGIC_1); wait(30, SC_NS); out2.write(SC_LOGIC_1); } } }; struct test_module : sc_module { SC_HAS_PROCESS(test_module); test_module(::sc_core::sc_module_name) { SC_THREAD(test_thread); } sc_port<sc_signal_in_if<sc_dt::sc_logic>, 2, SC_ZERO_OR_MORE_BOUND> prt_input; void test_thread() { // Create dynamic sensitivity list sc_event_or_list any_port; for (int i = 0; i<prt_input.size(); ++i) { any_port |= prt_input->value_changed_event(); } sc_dt::sc_logic data; int id; for (;;) { wait(any_port); for (int i = 0; i < prt_input.size(); ++i) { if (prt_input->event()) { data = prt_input->read(); id = i; std::cout << std::dec << "From port id " << id << " port[" << i << "] received " << "0x" << std::hex << data << " at " << sc_time_stamp() << std::endl; } } } } }; int sc_main(int argc, char** argv) { sc_signal<sc_dt::sc_logic> sig1; sc_signal<sc_dt::sc_logic> sig2; test_producer tprod{ "tprod" }; test_module tmod{ "tmod" }; tprod.out1(sig1); tmod.prt_input(sig1); tprod.out2(sig2); tmod.prt_input(sig2); sc_start(); return 0; } But, I am not sure I understood your second remark "to reduce the number of output ports (and hence signal) you might want to group signals logically belonging together into structs. Those can be used as data typs of signals and ports. This reduces the number of signals and events and increases simulation speed. " I am really interested in having a non-intrusive behaviour of that target module in terms of simulation speed mainly. It would be very helpful if can give an example of such logic groups of ports and signals on target side as you imagine(d) it. In my use case I have the pre-condition, that the initiator module is a 3rd party IP and I cannot restructure it using the logic groups as you proposed. Then, would it even make sense to have logic groups of input ports on target side only? Thanks in advance.
  6. Hello, I have an example of an initiator with large number of sc_out type of ports (let us say around 400). I need to model a target which should be bound to the different output signals of the initiator and handles their written values internally. To have a more generic and minimal code of such a target I thought that the best way is to have a multiport of type sc_port<sc_signal_inout_if<T>,N>, with number N is the number of outputs that the target should receive. I tried the following code with N=2 as a probe: struct test_producer : sc_module{ sc_out<sc_dt::sc_logic> out1; sc_out<sc_dt::sc_logic> out2; SC_HAS_PROCESS(test_producer); test_producer(::sc_core::sc_module_name){ SC_THREAD(test_prod); dont_initialize(); } void test_prod(){ while (1){ out1.write(SC_LOGIC_0); out2.write(SC_LOGIC_0); wait(10, SC_NS); } } }; struct test_module : sc_module { SC_HAS_PROCESS(test_module); test_module(::sc_core::sc_module_name) { SC_THREAD(test_thread); } sc_port<sc_signal_inout_if<sc_dt::sc_logic>, 2, SC_ZERO_OR_MORE_BOUND> prt_input; void test_thread() { // Create dynamic sensitivity list sc_event_or_list any_port; for (int i = 0; i<prt_input.size(); ++i) { any_port |= prt_input->value_changed_event(); } sc_dt::sc_logic data; int id; for (;;) { wait(any_port); for (int i = 0; i < prt_input.size(); ++i) { if (prt_input->event()) { data = prt_input->read(); id = i; std::cout << std::dec << "From port id " << id << " port[" << i << "] received " << "0x" << std::hex << data << " at " << sc_time_stamp() << std::endl; } } } } }; int sc_main(int argc, char** argv) { test_producer tprod{ "tprod" }; test_module tmod{ "tmod" }; tprod.out1(tmod.prt_input); tprod.out2(tmod.prt_input); sc_start(); return 0; } The code builds successfully, but I got the following error when running it: What I did wrong here and how can I model the interface of such a target efficiently? Shall I insert for instance any kind of converters between the initiator and the target? B.T.W. I thought as well about having and sc_vector type of inputs of my target module. But I am not sure how to bind an sc_vector type of port to each sc_out output port of my initiator and if that is even allowed. Any advise in this direction as well? Thanks in advance for the help.
  7. Hi David, Thanks first for your prompt and detailed response. Unfortunately I am using the SystemC 2.3.1. What is the best solution to capture the triggered event on the multiport and related port index in this case?
  8. Hello, When using a multiport port type as follows: struct M:sc_module{ sc_port<sc_signal_in_if<sc_dt::sc_logic>, 32, SC_ZERO_OR_MORE_BOUND> prt_input; void end_of_eleaboration(){ SC_METHOD(action); for(int i=0;i<prt_input.size();i++) sensitive << prt_input->value_changed_event(); } ... }; Is there any way to capture the port index "i" which changed the value and caused the method to be called? Thanks,
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