I know this will sound weird, but I will ask anyway :D
I have recently completed my first ASIC design(Front end and functional verification). Although I used some SystemVerilog constructs like functions and tasks and some other stuff, but really I verified whole digital part without UVM.
My question is: What are the advantages of UVM, and why UVM is needed in the first place, as it seems that tasks and functions can verify any design(it seems only, but I am not so much experienced).
Will learned members shed some light on it?
Thanks in advance and best wishes in fi