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akb20

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  1. The problem with your suggested solution is that it is not giving the correct latency value of the pipeline which is my only target. Note that I already know the latency (in terms of number of clock cycle) of the pipeline which is same as the number of stages. I also understood that FIFO is better way to do handshaking but the FIFO is not delaying in any pipeline stage. So there is no correct latency value. I think that only wait() can pause the simulation but it is only possible in SC_THREAD or SC_CTHREAD and not possible in SC_METHOD. Currently, if I change the SC_METHOD to SC_CTHREAD,
  2. I want to thank you for your reply. I could not understand your first solution. 1) Why do I need to put the txProcess at the first position? 2) What do you mean by controlling the order of calling? Actually, I am trying to implement two stages and want to see the latency difference compared to only one stage. I think the latency should increase. But currently there is no change of latency whether one or two stages. I thought that if I create two separate methods for two stages, it will take two clock cycles. But it is not true. Kindly suggest me how I can implement two stages a
  3. I have a design.h and design.cpp as given below. I am trying to have two stages in the design. I notice that the latency is same when I had only once stage. I don't understand why the number of clock cycles required by data to pass the design can remain same if I have two stages instead of one. I think that the two stages are not correctly done. //Design.h file #include <systemc.h> #include "Buffer.h" using namespace std; SC_MODULE(Design) { sc_in_clk clock; sc_in <bool> reset; sc_in <Flit> flit_rx[DIRECTIONS + 2]; sc_out <Flit> flit_tx[DIRECTIONS + 2]; Buffe
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