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  1. Hello David thanks so much for your quick answer, time and valuable support. The above code style show by you is really helpful for me and you are alright about it just work stricly for simulation purposes. But it works, making short size some of my header files and more esthetic. About the synthesis tool you are right up to my understanding, so I will give a try with another vendor HLS tool, cause that is something that I am trying to figure out with the actual project with the aim to get at the end a RTL from a relatively complex digital design in SystemC, but as you mention the standard is not enough to define how to implement, or may be not just the standard the vendors lag of a proper guidelines for this.
  2. Hello everybody, I was looking for a main topic about synthesizable SystemC here but there is not any one specific about it. I have been learning and working with SystemC to RTL, mostly modelling pure digital systems and trying to do it clock cycle accurate. The last project that I am working on is on model and implement a 32bit processor core. Until now the pure SystemC model is fulfilling the specifications and now I am trying to synthesize it with VIVADO HLS suite. I already checked Accellera Synthesis Subset 1.4.7 and many other kind of manuals or guidelines for that purpose. I am using SC_SIGNAL as channel between methods inside the same module I have the sc_signal defined as: sc_core::sc_signal<sc_dt::sc_bv<32> > register[32] and it is added to the sensitivity list in the following way: SC_METHOD(prc_assign_rf_reg); sensitive << register[0]; sensitive << register[1]; .... down to sensitive << register[32]; My question is somebody knows or have in mind some other way to implement the sensitivity list of this multidimensional signal array or could advice me another way to implemented, in order to firstly avoid to instance every array row position in the sensitivity list and secondly to implement this type of vector memory in another way. Thanks for your attention and support. Juan
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