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Gurmeet Singh Taank

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  1. Hi Eyck, I will be using this workaround(at the cost of one extra hierarchy). Regards, Gurmeet
  2. Eyck, Earlier bpad_10634.err error was due to the mismatching port widths, I corrected that issue. As per a document, Xcelium implements the IEEE1666-2011 standard for System-C which includes the sc_vector as well. I might be doing something wrong here on specific version usage or improper use of macros/command line options. I have raised a support ticket with Cadence on the sc_vector support in Xcelium. 1. Independently module is compiling with xrun –sysc –sv adder.cpp adder.v (please find the “module_standalone” file attached) xrun -sysc -sv -clean -disable_sem2009 adder
  3. Thanks Eyck, With the use of vectors, adder.v and adder.cpp are compiling successfully. However if I instantiate the adder.v into my TB its still throwing elaboration error. Please have a look at the attachments.
  4. Hi Experts, How to achieve the port binding for array of vectors in system-C constructors? I want to remove verilog modules and plug-in system-c modules into a big SV test-bench(basically to check the logic equivalence of SC model with RTL using RTL verification testcases). I cannot change the hierarchy of ports here(otherwise lots of RTL verification test cases may fail on the TB). I have already done this work for some modules and its working fine with Cadence Xcelium simulator. However some modules are using the array of bit vectors as their ports which I am not sure how to bind
  5. As long it is storing the right data in the memory you want to model; this behavior should be fine. If this would have been a purely asynchronous ram hardware this must have happened in the actaul hardware as well since it is imposible to align the edges of two indepedent buses(data and address here) below some practical limits of few pico seconds(however the first write may not settle properly in actual hardware). System-C is not for low level modeling, you should use it for modeling above the RTL level.If you still want to avoid this, one way would be to combine two different buses into sin
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