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Avnita

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  1. please advice me resolve this issue Info: (I804) /IEEE_Std_1666/deprecated: multiple () binding deprecated, use explicit port binding instead. Chronologic VCS simulator copyright 1991-2017 Contains Synopsys proprietary information. Compiler version N-2017.12-SP2-7; Runtime version N-2017.12-SP2-7; Nov 23 19:52 2019 at time15 ns::(a, b, cin):000(a, b, cin):00 simv: /home/avnita/Workspace/SYSTEM_C_FILES/adder_testbench.cpp:30: void testbench::process(): Assertion `COUT == SC_LOGIC_1' failed. An unexpected termination has occurred in ./simv due to a signal: Aborted Hostname
  2. Sir i have an doubt that when i compile any code in system c it generate simv file and i simulate it by using ./simv command but then i wrote new code and complie it , it got compiled the previous code and and showing the same output as previous one. Also in my systemc directory location it generate /csrs directory and inside csrc it generate /sysc directory and inside this it automatically generate .o and .a extention file. Sir could you please advice me on this and guide me that how I will get clear view about systemc. /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/half_adder.o:
  3. Hello sir, Again it through an error messange for this code #include "systemc.h" //AND gate module SC_MODULE (and_gate) { sc_in <bool> a, b; sc_out <bool> c; //Process for AND gate void and_fun() { c.write(a.read() & b.read()); } //Constructor for AND gate module SC_CTOR (and_gate) { SC_METHOD (and_fun); //process for sensitivity sensitive << a << b; } int sc_main(int argc, char* argv[]) { //return 0; } }; /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc
  4. Hello sir, I wrote and_gate systemc code with test bench and it got compiled, also generated simv but it shows Segmentation fault (core dumped) error. Could you please suggest me what exactly it is and how I will resolve this. #include "systemc.h" //AND gate module SC_MODULE (and_gate) { sc_in <bool> a, b; sc_out <bool> c; //Process for AND gate void and_fun() { c.write(a.read() & b.read()); } //Constructor for AND gate module SC_CTOR (and_gate) { SC_METHOD (and_fun); //pro
  5. I have written test bench for the above code (and gate) but i am getting some errors. Please guide me that how to write test bench in system C #include "systemc.h" #include "and_a.cpp" SC_MODULE (and_tb) { sc_in <sc_int <8> > a, b; sc_out <sc_int <8> > f; sc_in <bool> clk; void and_gate() { a.read(0); b.read(0); //f.write(0); wait(); a.read(1); b.read(1); //f.write(1); wait(); a.read(0); b.read(1); //f.write(0); wait(); a.read(1); b.read(0); //f.write(0); wait(); sc_stop(); } SC_CTOR (and_tb) { SC_METHOD (a
  6. Hello, Thankyou for your advice, I applied sc_main and I got this output mention below as screen shot.
  7. Hiiiii.........I wrote simple and gate code in system c and i am using vcs tool. could you please advice me that how do i complie this code, i follow these step to compile system c code on my tool: 1. syscan filename.cpp 2. vcs -sysc filename.cpp 3. ./simv #include "systemc.h" SC_MODULE(and_a) { sc_in < sc_uint <8> > a, b; sc_out < sc_uint <8> > f; sc_in <bool> clk; void comp_and() { f.write(a.read() & b.read()); } SC_CTOR(and_a) { SC_METHOD( comp_and ); sensitive <
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