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Everything posted by Narendra

  1. Hi , We are setting the Volatile bit to 1 for the "RO" type access registers fields using the configure task. Our understanding is that, some "RO" type status registers inside the design keep on changing during the simulation time and its need to be avoid checking with the default values when we run uvm_reg_hw_reset_seq test. But after setting this volatile bit set, we observed when we use update() function call at uvm_reg_block::update() the write calls are initiated for this RO registers apart with the RW registers where the mirrors values and desired values are not same. So is this behavior is expected ? What is the use of doing write calls to RO type registers ? Can you suggest me what are the use cases for the volatile bit set ? regards V Narendra D
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