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  1. Thank you everybody for your replies. I ended up implementing new Clock based on the default sc_clock (which I found here). I figured that it would be more efficient if I stack to the default implementation, rather than a SC_MODULE with a SC_THREAD in it (not sure about it yet).
  2. Thank you David, but I am interested in "turning off" clock temporarily, such that I can skip through IDLE periods in my simulation.
  3. Could you please clarify on how one can disable the clock? I have a Verilated RTL wrapped in a TLM AT. Please correct me if I am wrong, but I can't just put a clock gating in front of my RTL, because the events will still be generated. And I can't find a relevant method in sc_clock class to just disable the clock. Maybe I need to use dynamic sensitivity, but it is not desirable for me, due to the Verilated part (or I just don't know how it should be done). Ideally I would like to Suspend clock generation based on the PEQ in my target. Thanks in advance!
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