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Mat's Achievements


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  1. I managed to do this by defining the input port as sc_bv, i.e., sc_in<sc_bv<5>> inputPort; Then, using ".range()" I can select part of the port I need : inputPort.read().range(0:2);
  2. I have recently started using SystemC for my project. I would appreciate if someone could help me with following problem. How can I select part of input port in SystemC? In Verilog it can be done easily by choosing the required bits, e.g., inputPort[3:1] How can I do this in Systemc? I have defined an input port as follows sc_in < sc_int<5> > inputPort; What is the syntax to read bits e.g., [1:3] from inputPort like I did in Verilog? I tried few syntax like inputPort.read({1:3}) but no success.
  3. I have recently started learning SystemC and I have got an error with sensitivity list in "SC_METHOD". I am trying to implement a fifo and the error corresponds to following part of the code: SC_MODULE(fifo){ ... sc_int<8> rd_addr, wr_addr; ... void buffer_full(); ... SC_CTOR(fifo){ SC_METHOD(buffer_full); sensitive << rd_addr << wr_addr; } }; I get error when compiling the code and it complains about sensitivity list. I would appreciate if someone could let me know what is wrong with the sensitivity list. how should I make "buffer_full" process sensitive to the changes in rd_addr and wr_addr. I also tried following syntax to see if it works with single bit sensitivity but still no success sensitive << rd_addr[0]; Many thanks
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