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Everything posted by meah

  1. Hi, All I am curious the guided policy about write-only register. I am using UVM 1.1d library and refer their guides. In UVM User Guide : 5.5 Construncting a Register Model Table 7 - Pre-defined Field Access Policies There is a description as follows : Access Policy - WO ... Effect of a Read on Current Field Value : No effect. However, In UVM Class Reference Register Layer > Register Model > Fields > set_access There is a description as follows : ”WO” W: as-is, R: error It seems the description in above two documents are conflict. Which one is UVM's intense about write-only register? Or did I miss the page : above two things are pointing different things? In my opinion, the response on read transaction of write-only field/register have a dependency on Design. So I think the verification engineer should model the test scenario depend on design specification : The access policy should not limit the operation of design. Thanks,
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