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veeresh k

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  1. Thanks
    veeresh k reacted to David Black in where can i find solved textbook examples of sys.c fgu ?   
    I went and looked at the website where this stuff was supposed to be and found problems. I then dug around and found an archived copy, did a quick sanity check, and I've now published it on GitHub under github.com/dcblack/SCFTGU_BOOK
    As noted, I am working on a modern version, but time is limited.
     
  2. Like
    veeresh k reacted to maehne in where can i find solved textbook examples of sys.c fgu ?   
    I am afraid, this is a question, which only @David Black or one of his co-authors of the book can answer. As far as I can remember, I could never find the advertised online material under the URL mentioned in the book. Nevertheless, I still consider it one of the best books on the topic of SystemC.
  3. Like
    veeresh k reacted to Eyck in C++ class object bringing into systemC Hierarchy   
    Hi Aarthi,
    if you just need to get the currently active module when hitting a breakpoint in you C++ code you might use the following command (assuming you use gdb):
    x sc_core::sc_get_current_process_b()->get_parent()->name() (see also here: https://stackoverflow.com/questions/18078226/how-to-get-sc-module-name-of-the-current-running-module#18123785)
    What it does is it calles the SystemC kernel function sc_get_current_process_b() which returns a pointer to sc_process_b (the base class of of sc_method_process and sc_thread_process). Inheriting from sc_obejt it also has a name() method so you could also do
    x sc_core::sc_get_current_process_b()->name() which just returns the full hierarchical name of the process.
    HTH
    -Eyck
  4. Like
    veeresh k reacted to Roman Popov in sc_spawn and anthoer process   
    sc_spawn allows to create process during simulation runtime.  SC_* macro can be used only at elaboration time. Please read more details in IEEE SystemC standard.
    Here is small usage example:
    #define SC_INCLUDE_DYNAMIC_PROCESSES #include <systemc.h> SC_MODULE(spawn_demo) { SC_CTOR(spawn_demo) { SC_THREAD(static_thread); } void static_thread() { sc_spawn_options opts; sc_spawn([&]() { wait(1, SC_NS); cout << "spawned @ " << sc_time_stamp() << "\n"; }, "spawned_thread", &opts); wait(1, SC_NS); cout << "static @ " << sc_time_stamp() << "\n"; } }; int sc_main(int argc, char **argv) { spawn_demo demo0{"demo0"}; sc_start(); return 0; }  
  5. Like
    veeresh k reacted to David Black in SystemC Program: Variable changing its value automatically   
    Yes, SystemC is doing exactly what is supposed to do. Perfect behavior and standard reaction when you don't understand event driven simulators.
    In Verilog/SystemVerilog, this behavior is called non-blocking assignment (NBA). In VHDL, this is the behavior of a signal.
     
     
  6. Like
    veeresh k reacted to Eyck in SystemC Program: Variable changing its value automatically   
    When reading the signal 'inter' right after writing  to it (line 25 of the referenced code) you read the current value and not the scheduled (new) value. Writes to signals (as part of methods or threads) are executed in the evaluation phase of the simulation kernel while the value is assigned during the update phase of the kernel (see also https://ptolemy.berkeley.edu/projects/embedded/research/hsc/class/ee249/lectures/l10-SystemC.pdf?46).
    If you read a signal in the same evaluation phase you are writing to it, you will always get the current value, not the new (scheduled) value. If you have several assignments to the signal the last one will always win. I.e. lets assume you have a signale  and a thread like:
    void thread(){ sig.write(42); wait(0, SC_NS); // advance by 1 delta cycle sig.write(1); cout<<"Sig is "<<sig.read()<<std::endl; sig.write(2); cout<<"Sig is "<<sig.read()<<std::endl; sig.write(3); cout<<"Sig is "<<sig.read()<<std::endl; wait(SC_ZERO_TIME); // same as the last wait(), advance by 1 delta cycle cout<<"Sig is "<<sig.read()<<std::endl; } you will get the output:
    Sig is 42 Sig is 42 Sig is 42 Sig is 3 because the update to sig will only happen during the wait() call.
    I hope this answers your question.
  7. Like
    veeresh k reacted to AmeyaVS in SystemC Program: Variable changing its value automatically   
    Hello @YashJ,
    It is expected behavior.
    Here is a brief explanation:
    //... // Find the inline comments: while(true){ wait(); //< Wait for default event sensitivty(static sensitive event!). In you case it is in.value_changed() cout<<"\nIN = "<<in.read()<<" TIME" <<sc_time_stamp()<<endl; inter.write(in.read()); //< Write to the inter signal -> which means schedule and event for updating the sc_signal. cout<<"\nInter before wait= "<<inter.read()<<endl; wait(10,SC_NS); //< Relinquish control to the SystemC scheduler -> perform evaluate and update phase for all event scheduled. (Change sensitivity to dynamic scheduled after 10 ns) out.write(inter.read()); //< inter has the new value assigned at 3 lines before this statement. cout<<"\nInter after wait= "<<inter.read()<<endl; cout<<"\nOUT = "<<out.read()<<" TIME" <<sc_time_stamp()<<endl; cout<<"\nIN when outed = "<<in.read()<<endl; } ///.... Hope it helps.
    Regards,
    Ameya Vikram Singh
  8. Like
    veeresh k reacted to AmeyaVS in SystemC basic tutorial and examples   
    Hello @ajinkya_bankar,
    Can you let us know what all have you tried?
    and also, what is it you are looking at SystemC for RTL design or high-level modelling?
    Most of the examples though dated, require minimal changes to be fully functional, and you can quickly update them to
    Did you look at examples directory within the SystemC open source implementation available here.
    If you looking at SystemC RTL design then probably this book: SystemC Primer would be good though also a bit dated.
    In-case you are looking for using SystemC for high-level modelling your a find these references to be quite useful:
    SystemC: From Ground Up (Second Edition) SystemC Language Reference Manual(LRM) Hope these resources help.
    Regards,
    Ameya Vikram Singh
  9. Like
    veeresh k reacted to Eyck in beginner problems on fifo waveform   
    Hi,
    you cannot bind interface to e.g. a class implementing those interface. What you can bind are sc_port and sc_export. So you would need to change your declaration to
    sc_core::sc_port< sc_core::sc_fifo_out<int> > output1; sc_core::sc_port< sc_core::sc_fifo_in<int> > input1; But this is not going to solve your problem as you cannot trace an sc_core::sc_fifo_out interface. Tracing is only possible for elements having a value semantic which are variables of various types (primitive ones like int or composed ones coming with the SystemC library like sc_int or sc_bv) and signals (since they have also a value semantic).
    interfaces (like are sc_core::sc_fifo_in) are essentially description how to manipulate things and therefore not trace with a tracefile. Using SCV it would be possible to do so but requires implementing some glue code.
    BR
  10. Like
    veeresh k reacted to maehne in fifo waveform tracing   
    You need to be more precise in your problem description! You did not post the exact error message you might have obtained nor is your code example complete and self-contained. Therefore, any answer by us is mostly based on wild guessing. Please note that you will only actually see traces in your VCD files if actually events happened during your simulation. If your sc_module example constitutes your Design Under Verification, you are missing at least in the posted code snippet some stimuli generator, which would trigger any events.
    I suggest you that you get familiar with C++ and then start with a good introduction tutorial / book on SystemC before pursuing your own modeling attempts.
  11. Thanks
    veeresh k reacted to AmeyaVS in fifo example   
    Hello @veeresh k,
    There are multiple issues in the sample code provided by you.
    Here are the heavily modified version:
    // main.cpp #include<systemc> //< Notice not systemc.h #include"head1.h" #include"head2.h" int sc_main(int argc, char* argv[]) { sc_core::sc_fifo<int> fifo(10); //< sc_core namespace specifier writer w("writer"); reader r("reader"); w.out(fifo); r.in(fifo); sc_start(1000, sc_core::SC_NS); //< Run simulation for a limited time since no stopping condition are provided upfront. Also time is also specified in sc_core namespace. return 0; } //head1.h // Notice the HEADER GUARD #ifndef HEAD1_H_ #define HEAD1_H_ // Changed the header file to systemc instead of systemc.h #include<systemc> SC_MODULE(reader) { // sc_fifo_in_if is a abstract class from which you cannot create an object. // sc_fifo_in is derived from the above class which actually implements the read method. sc_core::sc_fifo_in<int> in; void roperation() { int val; while (true) { wait(10, sc_core::SC_NS); // Time unit is defined in sc_core namespace. for (int i = 0; i <= 15; i++) { in.read(val); std::cout << val << std::endl; //< when using the systemc header you need to specify the std namespace. // Or you can use the statement after including all the header files: // using namespace std } } std::cout << "Availaible : " << in.num_available() << std::endl; //< Instead of num available it is num_available //< when using the systemc header you need to specify the std namespace. // Or you can use the statement after including all the header files: // using namespace std } SC_CTOR(reader) //< Your code mentions here writer the constructor name should be same as the class name. { SC_THREAD(roperation); //< Your code mentions woperation } }; #endif // HEAD1_H_  
    //head2.h // Refer the head1.h for similar details #ifndef HEAD2_H_ #define HEAD2_H_ #include<systemc> SC_MODULE(writer) { // Refer the head1.h for similar details sc_core::sc_fifo_out<int> out; void woperation() { int val = 0; while (true) { wait(10, sc_core::SC_NS); for (int i = 0; i <= 20; i++) { out.write(val++); } } } SC_CTOR(writer) { SC_THREAD(woperation); } }; #endif // HEAD2_H_ Here is a minimal makefile for building the example:
    CC=gcc CXX=g++ CXX_FLAGS= -g3 -Wall -c all: main.exe main.exe: main.o ${CXX} $< -o $@ -L${SYSTEMC_HOME}/lib-linux64 -L${SYSTEMC_HOME}/lib -lsystemc main.o: main.cpp head1.h head2.h ${CXX} ${CXX_FLAGS} -I${SYSTEMC_HOME}/include -o $@ $< clean: rm -rf main.o main.exe Note:
    For reference of the sc_fifo_in/out_if classes see here. For more details you can also refer to the SystemC LRM.

    Hope it helps.

    Regards,
    Ameya Vikram Singh
  12. Like
    veeresh k reacted to AmeyaVS in Systemc 2.3.2 Changes   
    Hello @sumit_tuwien,
    You can find the necessary details from the SystemC sources.
    You can look into these files for more details:
    RELEASENOTES README NOTICE You can also compare the RELEASENOTES from previous releases.
    Regards,
    Ameya Vikram Singh
  13. Like
    veeresh k reacted to Eyck in clock generation in system c   
    The clock cycle is determined by the wait(1, SC_NS) statements withing the for loop. This defines the duration of the high and low phase of the clock you are seeing. The timesacel message comes from the VCD trace file (more specifically its writer) saying that the recording resolution will be teh default of 1ps which might be too small for some cases. You may ignore this message or explicitly set the VCD timescale.
    What Ameya is refering to is to replace the explicit clock generation with the SystemCs own sc_clock. This would alleviate you from describing the clock changes explicitly.
    Actually in my opinion this is a really bad example for several reasons:
    it bloats the sc_main function with testbench coder it mixes periodic signal change generation (the for loops) with functional code (writing reset and enable) it does not use SystemC utilities which make coding easier Best regards
  14. Like
    veeresh k reacted to AmeyaVS in clock generation in system c   
    Hello @veeresh k,
    This example does not have a dedicated clock generator.
    // These statements are what driving the clock signal to with High time of 1 ns and low time of 1 ns. for (i=0;i<10;i++) { clock = 0; sc_start(1, SC_NS);// Run simulation for 1 ns. clock = 1; sc_start(1, SC_NS);// Run simulation for 1 ns. } What message you receive from the SystemC kernel refers to the timescale of 1 ps e.g.:
    Info: (I702) default timescale unit used for tracing: 1 ps You can get the SystemC API documentation for the sc_clock from here:
    SystemC sc_clock api reference.
    If you need a sample you can find a use-case reference here(though a little bit-dated):
    https://github.com/AmeyaVS/SystemC_ramblings/blob/ff1a111063842bfcd6f5de6bb3db74917dc6331c/src/03_fir/firsytemmain.cpp#L26
    Hope it helps.
    Regards,
    Ameya Vikram Singh
  15. Thanks
    veeresh k reacted to David Black in system c beginner   
    Here is a short list of topics in no particular order you need to be comfortable with in order to be have an easier time learning SystemC:
    [Note: Others might chime in with variations on this list (add/subtract), and this is not necessarily a complete list, but I am fairly certain if you are able to comfortably use the topics I list below, you will have very little trouble syntactically with learning SystemC. In addition to C++, it helps if you have some familiarity with event driven simulation (e.g. SystemVerilog or VHDL). Also, if you have deep knowledge in another OO language (e.g. Java or SystemVerilog), you might have an easier time learning the C++ part.]
    Difference between declaration and definition Pass by value vs pass by reference Use of const (5 distinct cases) Casting C++ style (4 types) Implicit vs explicit conversions Use of function overloading and how to deal with ambiguity issues Use of std::string Use of streaming I/O How to declare, define and use classes Definition of default constructor Purpose and syntax of copy constructor How to declare and use namespaces Operator overloading as member functions and global functions. The difference between overloading and overriding. Relationship between class and struct How to extend classes and multiple inheritance Purpose of public and private Storage types and lifetimes: static, automatic, dynamic How to properly use new and delete Use of pointers and understanding of issues with pointer arithmetic Use of arrays and issues Advantages and use of std::vector<> Use of try-catch and throw Use of initializer list in constructor and a proper understanding of the order of construction Polymorphism and RTTI RAII Rule of 4 (6 if using C++11 or later) How and where to define templates/generic programming (does not need to be deep knowledge - just the basics) Use of templates and nested templates. Definition of full and partial template specialization. Different types of constructors and destructors Use of virtual inheritance (hint: it's not polymorphism) Extra topics:
    More STL including at least std::map<>, std::set<> Boost Modern C++ users (2011 onward) should know about:
    nullptr Uniform initialization Use of auto Use of ranged for Lambda definition, binding and use constexpr std::unique_ptr<>, std::shared_ptr<>
  16. Thanks
    veeresh k reacted to maehne in system c beginner   
    First, make sure that you are proficient in C++ as SystemC is a C++ library, which makes extensively use of advanced C++ features! Then, read a good introductory book on SystemC. I am personally not familiar with the SystemC Primer so cannot judge it. I found the book "SystemC from the Ground Up" by David C. Black, Jack Donovan et al. very helpful to learn SystemC.
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