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Everything posted by Eyck

  1. Hi Kevin, if you check here https://github.com/Minres/SystemC-Components/blob/master/incl/scc/utilities.h there are three macros which make live easier: #define TRACE_VAR(F, X) sc_core::sc_trace(F, X, std::string(this->name()) + "." #X) #define TRACE_ARR(F, X, I) sc_core::sc_trace(F, X[I], (std::string(this->name()) + "." #X "(" + std::to_string(I) + ")").c_str()); #define TRACE_SIG(F, X) sc_core::sc_trace(F, X, X.name()) They can be used with local variables and arrays as well with SystemC objects providing the name() funtion. This way tracing a signal becomes as easy
  2. Actually Sumit is right, you need to convert the string to a bit vector (sc_bv) of length string.lenght()*8. And here the problem starts: the sc_bv needs to have a constant lenght from the very beginning on and it cannot change during the simulation as the length is store in VCD at the very beginning of the file. In the viewing tool you can then select an interpretation of the bit vector to see a string. Best regards Eyck
  3. sc_signal only triggers an event if you write a value different from the current one. If you want to trigger events and hence invoke method/sc_thread you need to use sc_buffer instead of sc_signal. It is a drop-in replacement. Best regards
  4. When reading the signal 'inter' right after writing to it (line 25 of the referenced code) you read the current value and not the scheduled (new) value. Writes to signals (as part of methods or threads) are executed in the evaluation phase of the simulation kernel while the value is assigned during the update phase of the kernel (see also https://ptolemy.berkeley.edu/projects/embedded/research/hsc/class/ee249/lectures/l10-SystemC.pdf?46). If you read a signal in the same evaluation phase you are writing to it, you will always get the current value, not the new (scheduled) value. If you h
  5. You might have a look at https://github.com/Minres/SystemC-Components/blob/master/incl/scc/router.h. This one uses mixins to enhance the functionality of tlm::tlm_initiator_socket/tlm::tlm_target_socket but basically implementes what you are describing. An example how to use it can be found here: https://github.com/Minres/SystemC-Components-Test/blob/master/examples/simple_system/simple_system.cpp Best regards
  6. Hi, you cannot bind interface to e.g. a class implementing those interface. What you can bind are sc_port and sc_export. So you would need to change your declaration to sc_core::sc_port< sc_core::sc_fifo_out<int> > output1; sc_core::sc_port< sc_core::sc_fifo_in<int> > input1; But this is not going to solve your problem as you cannot trace an sc_core::sc_fifo_out interface. Tracing is only possible for elements having a value semantic which are variables of various types (primitive ones like int or composed ones coming with the SystemC library like sc_in
  7. The clock cycle is determined by the wait(1, SC_NS) statements withing the for loop. This defines the duration of the high and low phase of the clock you are seeing. The timesacel message comes from the VCD trace file (more specifically its writer) saying that the recording resolution will be teh default of 1ps which might be too small for some cases. You may ignore this message or explicitly set the VCD timescale. What Ameya is refering to is to replace the explicit clock generation with the SystemCs own sc_clock. This would alleviate you from describing the clock changes explicitly.
  8. Hi, it seems you lack a basic understanding of C/C++ visibility of variables. As fifog32 is declared a local variable in sc_main you can only access it in sc_main, it is unknow in any other function. BR
  9. Hi, These are the command line arguments argc and argv which are propagated from main(). See also https://stackoverflow.com/questions/3024197/what-does-int-argc-char-argv-mean#3024202 Best
  10. Hi, you need to be aware that SystemC does not run threads concurrently rather in an sequential manner. This means other threads and functions are only executed when your Next_event_thread() is suspended i.e. calls wait(). As long as code gets executed in the '-- // intercept here' region the rest of the simulation is suspended. This is no issue at all for the simulation. From your question I derive that you are going to implement a GUI on top of a simulation. Here it is a bad idea to run the GUI in the SystemC simulation (OS-)Thread. It would be better to create an OS-thread runni
  11. Whenever you call a generic protocoll function lile b_transport or nb_transport you supply an sc_time argument as reference so it can changed be the callee. This delay argument is the offset of the begin (when calling the function) or to the end (after the function returns) of this transaction to the current simulation time point. This is called timing annotation... Best regards
  12. Well, usually this describes the simulation timing behavior of a system. Approximately-timed models breakdown communication protocols into the subsquent phases with attached time points and durations. The components of a system adhere to a common or global time base - they execute in sync. In loosly-timed models part of the system are allowed to stick to their own time base which might deviate from the global time base by a given amount (the quantum). Communication transactions a handled as a single transaction with annoteted time points so that the components can react acccordingly. As
  13. Hi shanh, looking at the SystemC LRM: this is what happens in your example. The event is notified while another event is pending since your 2 threads sleep for the same amount of time. You would need to guard the event notification, use 2 separate events or an event queue similar to tlm_utils::peq_with_cb_and_phase. Best regards
  14. Hi, maybe I do not get the intent of your question but since SystemC is a C++ class library there is no separation between C++ and SystemC. What usually is separate are functional models and timed models as the latter one introduce a notion of time. As a functional model does not have this notion of time (only of sequence) care has to be taken to integrate a functional model into/with a timed model. Hope that helps
  15. Hi, when using CCI 0.9.0 with CLang 6.0 I get a compiler error: cci_broker_handle.h:139:42: error: calling 'get_param_handle' with incomplete return type 'cci::cci_param_untyped_handle' return cci_param_typed_handle<T>(get_param_handle(parname)); ^~~~~~~~~~~~~~~~~~~~~~~~~ This can be solved by a #include "cci_cfg/cci_param_typed_handle.h" at line 27 of cci_broker_handle.h. I have no clue how this works when using gcc (and it works :-S) Best regards -Eyck
  16. Hi Karthik, you need to provide a constant expression as template argument so that it can be evaluated at compilation time. See http://en.cppreference.com/w/cpp/language/constant_expression. and http://en.cppreference.com/w/cpp/language/template_parameters#Template_non-type_arguments. So it would need to be written as: const int WDW_SIZE = 2; Best regards -Eyck
  17. Well, the '\' escapes the newlines at the end of each line so that the compiler treats all lines as a single line. '#define' is a pre-processor command which expects everything to be on a single line. If you do not escape the newlines then your code is one several lines and does not work anymore. HTH -Eyck
  18. Hi katang, I cannot comment on 3./ but item 1./ and 2./ (dynamic_cast) is generally fine (at least from a simulation point of view). Wrt. to item 4./ this is a C++ mechanism which you do not really obey. If you construct the base class the virtual function pointer in the vtable of the class point to MWEbase::Initialize_method(). Hence you register the pointer to this method with the SystemC kernel. But this is easy to work around. Basically you register a dispatch function with the SystemC kernel which calls then the virtual function: void Dispatch_initialize_method(void)
  19. Hi, if you want to map the Verilog initial block you can use the start_of_simulation() callback function. This one us called automatically by the kernel at simulation start. But you cannot call wait() either in this function. If you need to execute somethin delayed you can post a sc_event in the start_of_simulation() function and register a method/trhead being sensitive to this event. Cheers
  20. You may use a temporary object: My::My(sc_core::sc_module_name nm, int ID) : sc_core::sc_module(sc_core::sc_module_name((string(nm).append(1,ID<26 ?'A'+ID : 'A'+ID +6)).c_str())) But I would move the stuff into a free function: sc_core::sc_module_name concatenate(sc_core::sc_module_name nm, int ID){ std::string res(nm); res.append(1,ID<26 ? 'A'+ID : 'A'+ID+6); return res.c_str(); } My::My(sc_core::sc_module_name nm, int ID) : sc_core::sc_module(concatenate(nm, ID)) This makes the whole code easier to understand and more maintainable... Cheers
  21. Hi Sumit, both options will forward your transaction only to the first bound initiator socket of your multi_passthrough_target_socket as it just calls the operator->() of the underlying port. What you want to do is: for(unsigned int i=0; i<In.size(); ++i) In[i]->invalidate_direct_mem_ptr(...) But here you forward the call to all initiator sockets. In case of invalidate_direct_mem_ptr() this might be ok but for nb_transport_bw() it isn't as the call is part of the AT phases protocol and then you send e.g a BEG_RESP to a socket which never sent a BEG_REQ thus violating
  22. Hi Sumit, you can use the size() method on both sockets to get the number of bound sockets. Cheers -Eyck
  23. Hi Sumit, of course it is allowed to bind an initator to a target socket, otherwise you would not be able connect an initiator to a target. But a can only once do this so usually you do it at the top level of connectivity. The picture below illustartes this, between module1 and module2 you have a binding of intor to target. +------------------------+ +----------------------+ | +---------------+ | | | | | | | | +-------------+ | | | | | | | | | |
  24. Maybe a little bit late but there are socket implementations available which do trace tlm transactions int a SCV database. They can be found at https://github.com/Minres/SystemC-Components/tree/master/incl/scv4tlm and are used e.g. at https://github.com/Minres/SystemC-Components/blob/5f7387ab7e3dfc2ff6a7cac6fbe834ed7ec8ae36/incl/sysc/tlmtarget.h which in turn serve as building blocks in https://github.com/Minres/SystemC-Components-Test/tree/master/examples/simple_system The setup given by Kai is put into sysc::tracer where all the tracing setup (VCD & SCV) is impelemted. Best reg
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