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  1. Hi, For rounding, take the deleted bits, add the msb of that to the value. If you want to know how all the specs for all rounding modes, please refer to table 46 in IEEE1666-2011 standard. regards, Fred
  2. Hi guys, thanks for the reply. i agree wait_until is exactly what i'd need here (with support for multiple resets) Long time ago, was there a wait_until() (implemented as a do/watching) constructs that got deprecated? regards, Fred
  3. Hi all, question about sc threads and events: In a Testbench monitor, i have something like this: SC_HAS_PROCESS(Monitor); Monitor(const sc_module_name& n) : Monitor_base(n) { SC_THREAD(proc); sensitive << clk.pos(); async_reset_signal_is(as_rst_n,false); reset_signal_is(rst_n,false); } Somewhere deep in proc(), there is a wait like this: wait(some_signal.negedge_event()); During the simulation, a synchronous reset is issued while proc() is waiting on the abovee negedge_event. The reset is missed by proc(). This behavior is exhibited by both accellera and commercial simulators. I can easily re-write the code to a do-while loop and resovle the issue, but was just wondering, is this by design. Is waiting on a specific event overriding all reset specs - is this by design or could this be revisited? thanks and regards, Fred
  4. Hi, Sumit, can you provide code example. thanks and regard,s Fred
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