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    campo85 reacted to Roman Popov in SystemC and latency simulation   
    If your pipeline is simple, like:  get data ->  process  data -> put data, without I/O operations on internal pipeline stages, then you can model latency while keeping throughput: just put output data into fifo-like channel that will delay output for N cycles.
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    campo85 reacted to Roman Popov in SystemC and latency simulation   
    No, there is no elegant way to simulate pipelines in SystemC.  Commonly you just write a separate thread for each pipeline stage. Like you will do in Verilog/VHDL. 
    1) All HLS tools I've used do not convert SC_METHODs to pipelines. Only SC_THREADs can be converted to pipelines, if they follow some vendor-specific restrictions.
    2) Yes, you can simulate latency by adding wait(N) to clocked SC_THREAD. However it will not simulate throughput. 
    In general, this is a well known problem that HLS-generated code changes timing (expressed in clock cycles) of design. So HLS-generated code can even fail in tests that were working on input SystemC code. To avoid this, your inter-thread communication mechanisms should not depend on latency and throughput of generated hardware. You can also create latency/throughput constraints for HLS tool.
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    campo85 reacted to maehne in sc_bitref usage   
    The compiler has difficulties to decide which overload of the assignment operator it should use. You can help him by doing a static_cast<bool>(myint[7]).
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    campo85 reacted to Roman Popov in How to model a delay line in SystemC   
    I've needed it for test environment modeling purposes, not for synthesis.
    Delta delay problems (also known as Shoot-thru) are possible in synthesizable SystemC. Common case is when you have a clock gate that inserts a delta delay into a clock signal distribution network. 
    However in SystemC it is solved in a different way: Instead of delaying all assignments, you use immediate notifications inside clock signal, so that processes sensitive to gated clock are executed in the same delta cycle with processes sensitive to ungated clock.
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