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enchanter

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  1. Hi Philipp: Thanks for your reply. The solution works perfect for me. But from my very basic C++ knowledge, I think 'static' means share the variable with all the instances of the class. So that means the 't1' and 't2' should share 'depth', 'depth_a', and 'depth_b'. And the 'const' means no one can change it. Then I am confused that how could 't1' and 't2' get different value of 'depth' and 'depth_x'?
  2. I have a top level module with template like this: template <int TOP_DEPTH=10> SC_MODULE(my_top){} And I have several sub modules like this: template <int DEPTH=10> SC_MODULE(sub_module_xxx> I try to instantiate sub modules with the modified DEPTH from top level: const int DEPTH_MODULE_A = <math1 on TOP_DEPTH> const int DEPTH_MODULE_B = <math2 on TOP_DEPTH> ... sub_module_a<DEPTH_MODULE_A> *pSubModuleA; sub_module_b<DEPTH_MODULE_B> *pSubModuleB; ... I got compile error about "invalid use of non-static data member". I am not sure what's the right way to do it in C++. (I don't want DEPTH_MODULE_xxx to be static, because my top_module may be used as submodule in other project with different value of TOP_DEPTH. )
  3. Thanks for your reply. I used verilog before and I think systemc is make for modeling hardware behaviour otherwise you can use c/c++. And also the SystemC module could possible connected with verilog module during the mix-language verification. So it is hard for me to not compare it with verilog. I know the range operator and it should work with bit vector. But I think I can't do it in sc_main because it will not be a thread and will not be updated on events like clock pos and signal toggling, right?
  4. 1 -> I don't mean sc_start(). I just don't know what's initial state of your sensitive list. Do they have any change at initial time to trigger your thread? 2 -> I think even in Verilog, it does matter. You logic is combinational logic, if the output can trigger the "+1" logic, you will have infinite loop, right?
  5. Maybe you can try to use: popo_out.write(popo_out.read() + popo_in.read()); in your while loop. But another things I am not usre are: 1. If your popo_clk_gen will be triggered? The sensitive list seams no toggling at beginning. 2. Does the output (sc_out) can be used as sensitive signal?
  6. I have a module's output is for example 20 bits. And it should be connected to other two modules' input which is 10 bits. Can I do it in sc_main or I have to create another module to do it? I expect something like assign in Verilog: din_a[9:0] = w_dout[19:10]; din_b[9:0] = w_dout[9:0];
  7. Do we need to release the memory created by "new" in SystemC? If yes, where is the best place to do it?
  8. This is also the question I keep asking and not find good answer yet. But I found an article from here: http://www.vip-central.org/2012/09/parameterized-interfaces-and-reusable-vip-part-3/ I thin it is good. But still a little bit complicated for me. Hope better solution for this.
  9. In my case (no uvm_reg),I have to pull a status register from DUT and do the next action base on the respond. My sequence body task: virtual task body(); do begin wait(wait_time); // initial is 1us, defined in new function. `uvm_do_with(req, {access_kind == READ; len == 1; addr == (cfpga_status_reg/2); }) get_response(rsp); wait_time = wait_time * 2; end while ((rsp.dio[0] & 'h00ff) < 'h00FF); endtask : body From my simulation, the rsp.dio[0] =0x009f, and it keep pulling the DUT register without wait for WAIT_TIME. And then the simulation stopped after several pullings (no time in my environment). I don't know why it doesn't wait. And anyone have better solution for this case? Thanks.
  10. I try to use uvm_tlm_analysis_fifo in my scoreboard. uvm_analysis_export #(spi_adc_item) before_export; uvm_analysis_export #(cpu_item) after_export; uvm_tlm_analysis_fifo #(spi_adc_item) before_fifo; uvm_tlm_analysis_fifo #(cpu_item) after_fifo; function void build_phase(uvm_phase phase); before_fifo = new("before_fifo", this); before_export = new("before_export", this); after_fifo = new("after_fifo", this); after_export = new("after_export", this); endfunction // build_phase function void connect_phase(uvm_phase phase); before_export.connect(before_fifo.analysis_export); after_export.connect(after_fifo.analysis_export); endfunction : connect_phase The before_fifo should have 8 items before the after_fifo is written one item. If I try to use before_fifo.get every time when item is written into, I can see all the item are good.: forever begin before_fifo.get(before_txn); $display("SPI_ADC_ITEM: %s", before_txn.sprint()); end But if I wait until after_fifo is not empty, the items get from before_fifo are all the last one be written into. forever begin after_fifo.get(after_txn); fifo_usage = before_fifo.used(); $display("Usage of before_fifo: %0d", fifo_usage); for (int i = 0; i < fifo_usage; i++) begin before_fifo.get(before_txn); before_txn.pack_ints(num_bits); $display("SPI_ADC_ITEM: %s", before_txn.sprint()); $display("Usage of before_fifo: %0d", before_fifo.used()); end end Log file: # UVM_INFO ../../src/spi_adc_monitor.sv(39) @ 10: uvm_test_top.sample_tb0.spi_adc0 [uvm_test_top.sample_tb0.spi_adc0] Transfer collected : # ----------------------------------------------------------------- # Name Type Size Value # ----------------------------------------------------------------- # spi_adc_item spi_adc_item - @548 # dout sa(integral) 4 - # [0] integral 1 'h0 # [1] integral 1 'h0 # [2] integral 1 'h1 # [3] integral 1 'h0 # len integral 32 'h4 # ----------------------------------------------------------------- # # UVM_INFO ../../src/spi_adc_monitor.sv(39) @ 30: uvm_test_top.sample_tb0.spi_adc0 [uvm_test_top.sample_tb0.spi_adc0] Transfer collected : # ----------------------------------------------------------------- # Name Type Size Value # ----------------------------------------------------------------- # spi_adc_item spi_adc_item - @548 # dout sa(integral) 4 - # [0] integral 1 'h0 # [1] integral 1 'h1 # [2] integral 1 'h1 # [3] integral 1 'h0 # len integral 32 'h4 # ----------------------------------------------------------------- # # FIFO Usage: 2 # SPI_ADC_ITEM: 'h6000 # FIFO Usage: 1 # SPI_ADC_ITEM: 'h6000 I pack the dout to integer so '0110' show '6' at the MSB. I have no idea what's wrong in my code. I attached my rubbish test code. Would please anyone give it look. Thanks
  11. I tried with "local" and it works great. Thank you very much, dave.
  12. Tried virtual sequence according to the example from verification academy. It works. But I met a scope problem with same variable name during try it. For example: 1. I defined "rand int unsiged number_of_samples" in my sample_transaction extends uvm_sequence_item) 2. I defined the sample variable "rand int unsigned number_of_samples" in my sample_base_seq extends uvm_sequence#(sampel_transaction) 3. I try to use "`uvm_do_with(req, {req.number_of_samples == number_of_samples;})" in sample_base_seq 4. I random the number_of_samples in virtual_seq extends uvm_sequence #(uvm_sequence_item) in this way: task body(): sample_base_seq sampel_seq; sample_req = sample_base_seq::type_id::create("sample_req"); sample_req.randomize() with {number_of_samples inside { [2:5];}; sample_req.start(sample_port, this); ... The sample_req.number_of_samples is generated properly (all the value hit in 2~5). But the sequence item pass to the driver is not, i got random number_of_samples value outside range [2:5]. If I change the name "number_of_samples" in the sample_base_seq to other name, it works great. I think it may be the scope issue that the simulator can't get the proper value for the "`uvm_do_with()". But I can't figure out what's wrong I did in my source code.
  13. My DUT has two interfaces. They are connected to different agents (agentA and agentB). The agentA will generate request to ask DUT to generate several data, then agentB will read it back. My question is how could I pass the number_of_gen_data from agentA's sequence_item to agentB's sequence_item for agentB to get right number of generated data? Or I should use other way instead of control agentB's sequnce_item? Thanks
  14. I try to write my first UVM verification test environment, but I found the test is stopped before the sequencer drop_objection. I highlight when the sequencer raise objection and when it drop it. But another highlight is [TEST_DONE] which happened before sequencer drop objection. I have no idea why it happened and any could have a look to it. Thanks. # UVM_INFO ../src/sample_env.sv(66) @ 0: uvm_test_top.sample_tb0.sample_env0 [RUN] Starting up 'uvm_test_top.sample_tb0.sample_env0' # UVM_INFO ../../lib/sample_pkg/sample_agent.sv(40) @ 0: uvm_test_top.sample_tb0.sample_env0.agent [RUN] String up 'uvm_test_top.sample_tb0.sample_env0.agent' # UVM_INFO verilog_src/uvm-1.1a/src/base/uvm_objection.svh(1120) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase # UVM_INFO ../../lib/sample_pkg/sample_seq_lib.sv(19) @ 0: uvm_test_top.sample_tb0.sample_env0.agent.sequencer@@sample_quick_test_sequence [sample_quick_test_sequence] sample_quick_test_sequence pre_body() raising main objection ... # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(54) @ 157833000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [DRIVER] @(6) 9018 # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(54) @ 158015000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [DRIVER] @(7) c907 # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(62) @ 158067000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [cpu_driver] Dropping objection # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(38) @ 158067000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [cpu_driver] Raising objection # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(41) @ 160870000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [DRV] Sample Number = 1 # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(54) @ 160979000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [DRIVER] @(0) 21f0 # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(62) @ 161031000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [cpu_driver] Dropping objection # UVM_INFO verilog_src/uvm-1.1a/src/base/uvm_objection.svh(1120) @ 161031000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase # UVM_INFO ../../lib/sample_pkg/sample_driver.sv(46) @ 161090000: uvm_test_top.sample_tb0.sample_env0.agent.driver [DRIVER] item = Sample Number = 6, Sample Delay = 10 # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(38) @ 161090000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [cpu_driver] Raising objection /top/uANA_RAMP_MON/uSAMPLE_DATA_BUFFER/U0/native_mem_module/mem_module/async_coll # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(41) @ 185670000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [DRV] Sample Number = 6 # UVM_INFO ../../lib/cpu_pkg/cpu_driver.sv(54) @ 185783000: uvm_test_top.sample_tb0.sample_env0.cpu_drv [DRIVER] @(0) 43c # UVM_INFO ../../lib/sample_pkg/sample_seq_lib.sv(30) @ 185870000: uvm_test_top.sample_tb0.sample_env0.agent.sequencer@@sample_quick_test_sequence [sample_quick_test_sequence] sample_quick_test_sequence post_body() dropping main objection # UVM_INFO ../src/sample_base_test.sv(33) @ 185870000: uvm_test_top [test_10_seq_item] ** UVM TEST PASSED **
  15. My question is if I can try to not use `#1ns` in the "hello_world" example? Because I think in some cases, I can't predict how long the simulation is needed. And I also want it to be ended as soon as possible. I tried the task run_phase(uvm_phase phase); phase.raise_objection(this); uvm_top.print_topology(); phase.drop_objection(this); endtask It doesn't work very well. I also put the raise/drop inside the producer and consumer. I got timeout.
  16. Thanks for the way to interpreted with example. But I notice that you are using uvm_test_done instead of phase. Could I know what's the difference between them? I just try the hello_world example in UVM-1.1. That use specific time "1us" to end the test. I try to use raise/drop objection in both producer/consumer/top modules. But I got timeout of 9200 seconds error. Can anyone show me how should I end the test without put specific time in it? thanks.
  17. ~/tmp/uvm-1.1/examples/simple/basic_examples/event_pool$ make -f Makefile.questa all make -f Makefile.questa BITS=32 dpi_lib make[1]: Entering directory `~/tmp/uvm-1.1/examples/simple/basic_examples/event_pool' mkdir -p ../../../../lib gcc -m32 -fPIC -DQUESTA -g -W -shared -x c -I/include ../../../../src/dpi/uvm_dpi.cc -o ../../../../lib/uvm_dpi.so In file included from ../../../../src/dpi/uvm_dpi.cc:33:0: ../../../../src/dpi/uvm_regex.cc:26:22: fatal error: vpi_user.h: No such file or directory compilation terminated. make[1]: *** [dpi_lib] Error 1 make[1]: Leaving directory `~/tmp/uvm-1.1/examples/simple/basic_examples/event_pool' make: *** [dpi_lib32] Error 2 Does anyone knows how to fix it?
  18. Is it there any tools can generate the register file for both RTL and UVM? Otherwise we still need to maintain two separated parts.
  19. What's difference between the simulation with or without "+define+UVM_NO_DPI" ? What's difference between the two solution? 1. Add +define+UVM_NO_DPI 2. Follow the examples/simple/phases/run_test/Makefile.questa (or any other simple examples). Please note your gcc/g++ version, the code would not work with older GCC (mine is gcc-4.3.2)
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