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AmeyaVS

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  1. Like
    AmeyaVS got a reaction from mo_ayman in Systemc-2.3.1 Installation problem on Windows 7 with Cygwin   
    Hello @mo_ayman,
    Well you could get it early for review comments from the people in SystemC LWG.
    Plus people with similar setup to yours can also take a jab at it in getting it fixed.
    Regards,
    Ameya Vikram Singh 
  2. Like
    AmeyaVS got a reaction from maehne in binding issue   
    Hello @Partha,
    As the error message suggests the third indexed interface in host(my_host) object instance is not bound:
    i.e. host_port.
    For future reference pass the name of the interface also so that you  can get more descriptive names in the error messages.
    For e.g.: Changing your source files as shown below changes the error message:
    // Code your testbench here. // Uncomment the next line for SystemC modules. #include <systemc.h> #include <stdlib.h> class slave_if : public sc_interface { public: virtual void write(int data) = 0; virtual void read() = 0; }; SC_MODULE(Host) { sc_in<bool> scl{"scl"}; sc_in<bool> sda{"sda"}; sc_in<bool> rw{"rw"}; sc_port<slave_if> host_port{"host_port"}; int val; void behaviour() { if (scl == 1 && sda == 0 && rw == 0) { val = rand() % 50; host_port->write(val); } else if (scl == 1 && sda == 0 && rw == 1) { host_port->read(); } } SC_CTOR(Host) { SC_METHOD(behaviour); sensitive << scl << sda << rw; } }; SC_MODULE(Master), public slave_if { sc_in<bool> clk{"clk"}; sc_out<bool> scl{"scl"}; sc_out<bool> sda{"sda"}; sc_out<bool> rw{"rw"}; sc_fifo_out<int> master_write_fifo{"master_write_fifo"}; sc_fifo_in<int> master_read_fifo{"master_read_fifo"}; int i = 0, data_get, val, no_bits = 8; Host my_host; void write(int data) { while (no_bits != 0) { sda = data & 1; wait(SC_ZERO_TIME); master_write_fifo.write(sda); no_bits++; } } void read() { while (i != 8) { master_read_fifo.read(val); data_get = data_get + (val * pow(2, i)); /*master_read_fifo.read(val); cout<<"value:->"<<val<<endl;*/ i++; } cout << "my data:-->" << data_get; } SC_CTOR(Master) : my_host("my_host") { my_host.scl(scl); my_host.sda(sda); my_host.rw(rw); } }; SC_MODULE(Slave) { sc_inout<bool> scl{"scl"}; sc_inout<bool> sda{"sda"}; sc_inout<bool> rw{"rw"}; Master slave_master; SC_CTOR(Slave) : slave_master("slave_master") { slave_master.scl(scl); slave_master.sda(sda); slave_master.rw(rw); } }; int sc_main(int argc, char *argv[]) { sc_clock clk("clk", 1, SC_NS); sc_signal<bool> scl{"scl"}; sc_signal<bool> sda{"sda"}; sc_signal<bool> rw{"rw"}; sc_fifo<int> main_fifo{"main_fifo"}; Master master("master"); master.clk(clk); master.master_write_fifo(main_fifo); master.master_read_fifo(main_fifo); Slave slave("slave"); scl.write(1); sda.write(0); rw.write(0); slave.scl(scl); slave.sda(sda); slave.rw(rw); sc_start(); return 0; } to
    SystemC 2.3.4_pub_rev_20190904-Accellera --- Nov 18 2019 21:47:55 Copyright (c) 1996-2019 by all Contributors, ALL RIGHTS RESERVED Error: (E109) complete binding failed: port not bound: port 'slave.slave_master.my_host.host_port' (sc_port) In file: /home/ameyavs/apps/src/systemc/src/sysc/communication/sc_port.cpp:235 Hope this helps.
    Regards,
    Ameya Vikram Singh
  3. Like
    AmeyaVS got a reaction from Philipp A Hartmann in error in systemc.h 118:16 error std::gets is not declared using std::gets   
    @daveW you can tryout the SystemC 2.3.2 draft release which fixes most of the issues while building under C++11/C++14 compilers.
    Have a look here:
    Regards,
    Ameya Vikram Singh
  4. Thanks
    AmeyaVS got a reaction from Roman Popov in What is SystemC library special in?   
    Hello @Elvis Shera,
    It seems your SystemC library has been build with different C++ standard flag.
    Can you post the output of following commands?:
    # Compiler version you are using g++ -v # Library Properties: nm -C $SYSTEMC_HOME/lib-linux64/libsystemc.so | grep api_version Regards,
    Ameya Vikram Singh
  5. Like
    AmeyaVS got a reaction from swami-cst in Compilation Error: error: std::gets has not been declared   
    Hello @kallooran,
    What version of SystemC library are you using?
    This issue has been fixed in the release of SystemC-2.3.2.
    You can find the latest release of SystemC-2.3.3 here: http://accellera.org/downloads/standards/systemc
    Hope it helps.
    Regards,
    Ameya Vikram Singh
  6. Thanks
    AmeyaVS got a reaction from kallooran in Compilation Error: error: std::gets has not been declared   
    Hello @kallooran,
    What version of SystemC library are you using?
    This issue has been fixed in the release of SystemC-2.3.2.
    You can find the latest release of SystemC-2.3.3 here: http://accellera.org/downloads/standards/systemc
    Hope it helps.
    Regards,
    Ameya Vikram Singh
  7. Like
    AmeyaVS got a reaction from re1418ma in Behavioral XOR Gate with Delay   
    Hello @re1418ma,
    You can look at this example:
    http://forums.accellera.org/topic/5678-clock-to-q-propagation-delay/?do=findComment&comment=13657
    Or this one which shows how to add delay in full adder:
    http://forums.accellera.org/topic/5715-delaying-simulated-execution/?do=findComment&comment=13844
    Hope it helps.
    Regards,
    Ameya Vikram Singh
  8. Like
    AmeyaVS got a reaction from re1418ma in Behavioral XOR Gate with Delay   
    Hello @re1418ma,
    This has been already discussed before here:
    http://forums.accellera.org/topic/5715-delaying-simulated-execution/
    Hope it helps and if you have further questions please feel to ask.
    Regards,
    Ameya Vikram Singh
  9. Like
    AmeyaVS reacted to Eyck in Need understanding of SystemC model use-cases   
    Well, this topic could fill an entire book...
    If you implement a model the first question you should as is: What is the purpose of the model? Which questions should the simulation of the model answer?
    Looking at architectural exploration which goes quite often hand in hand with performance analysis the question is: does my HW/SW split and my HW partitioning satisfy my perfomance requirements (wrt. latency, thru-put, compute.efficiency, power,...). In this case you usually do not need to implement a particular functionality in detail rather something that 'behaves like' in terms of your requirements. E.g. if you need to check that your communication scheme (buses, arbiters, bridges etc.) fulfills the needed band with you use traffic generators but have a fairly accurate bus model, sometimes even at AT. And you need to implement the mechanisms to observer and extract the needed performance indicators to allow the analysis
    For software development the requirements are different. Here the maximum simulation speed is required so whereever possible you take short cuts. Bus transaction are not modelled anymore rather DMI is used (of course if functionality allows to do so e.g. when reading from/writing to a memory) and the entire model may run in LT mode which allowes parts to independently advance in time. Peripheral units may be modelled register-accurate but with out real functionality, i.e. a system control unit does not follow the needed scheme if changing e PLL frequency and alike.
    This might give you some high-level clue. There are many more things to it but all of them depend on the answer to the initial questions.
    Maybe the DCVon Europe 2017 tutorial on virtiual protorypes might provide a few more answers. You may find a PDF version of it at the MINRES site in the Publications and Papers section or at https://minres.com/downloads/VP_Tutorial_DVCon-2017.pdf as well as at the DVCon Europe website https://dvcon-europe.org/conference/history
    Best regards
    -Eyck
  10. Like
    AmeyaVS got a reaction from veeresh k in SystemC Program: Variable changing its value automatically   
    Hello @YashJ,
    It is expected behavior.
    Here is a brief explanation:
    //... // Find the inline comments: while(true){ wait(); //< Wait for default event sensitivty(static sensitive event!). In you case it is in.value_changed() cout<<"\nIN = "<<in.read()<<" TIME" <<sc_time_stamp()<<endl; inter.write(in.read()); //< Write to the inter signal -> which means schedule and event for updating the sc_signal. cout<<"\nInter before wait= "<<inter.read()<<endl; wait(10,SC_NS); //< Relinquish control to the SystemC scheduler -> perform evaluate and update phase for all event scheduled. (Change sensitivity to dynamic scheduled after 10 ns) out.write(inter.read()); //< inter has the new value assigned at 3 lines before this statement. cout<<"\nInter after wait= "<<inter.read()<<endl; cout<<"\nOUT = "<<out.read()<<" TIME" <<sc_time_stamp()<<endl; cout<<"\nIN when outed = "<<in.read()<<endl; } ///.... Hope it helps.
    Regards,
    Ameya Vikram Singh
  11. Like
    AmeyaVS reacted to Eyck in SystemC Program: Variable changing its value automatically   
    When reading the signal 'inter' right after writing  to it (line 25 of the referenced code) you read the current value and not the scheduled (new) value. Writes to signals (as part of methods or threads) are executed in the evaluation phase of the simulation kernel while the value is assigned during the update phase of the kernel (see also https://ptolemy.berkeley.edu/projects/embedded/research/hsc/class/ee249/lectures/l10-SystemC.pdf?46).
    If you read a signal in the same evaluation phase you are writing to it, you will always get the current value, not the new (scheduled) value. If you have several assignments to the signal the last one will always win. I.e. lets assume you have a signale  and a thread like:
    void thread(){ sig.write(42); wait(0, SC_NS); // advance by 1 delta cycle sig.write(1); cout<<"Sig is "<<sig.read()<<std::endl; sig.write(2); cout<<"Sig is "<<sig.read()<<std::endl; sig.write(3); cout<<"Sig is "<<sig.read()<<std::endl; wait(SC_ZERO_TIME); // same as the last wait(), advance by 1 delta cycle cout<<"Sig is "<<sig.read()<<std::endl; } you will get the output:
    Sig is 42 Sig is 42 Sig is 42 Sig is 3 because the update to sig will only happen during the wait() call.
    I hope this answers your question.
  12. Like
    AmeyaVS got a reaction from veeresh k in SystemC basic tutorial and examples   
    Hello @ajinkya_bankar,
    Can you let us know what all have you tried?
    and also, what is it you are looking at SystemC for RTL design or high-level modelling?
    Most of the examples though dated, require minimal changes to be fully functional, and you can quickly update them to
    Did you look at examples directory within the SystemC open source implementation available here.
    If you looking at SystemC RTL design then probably this book: SystemC Primer would be good though also a bit dated.
    In-case you are looking for using SystemC for high-level modelling your a find these references to be quite useful:
    SystemC: From Ground Up (Second Edition) SystemC Language Reference Manual(LRM) Hope these resources help.
    Regards,
    Ameya Vikram Singh
  13. Thanks
    AmeyaVS got a reaction from veeresh k in fifo example   
    Hello @veeresh k,
    There are multiple issues in the sample code provided by you.
    Here are the heavily modified version:
    // main.cpp #include<systemc> //< Notice not systemc.h #include"head1.h" #include"head2.h" int sc_main(int argc, char* argv[]) { sc_core::sc_fifo<int> fifo(10); //< sc_core namespace specifier writer w("writer"); reader r("reader"); w.out(fifo); r.in(fifo); sc_start(1000, sc_core::SC_NS); //< Run simulation for a limited time since no stopping condition are provided upfront. Also time is also specified in sc_core namespace. return 0; } //head1.h // Notice the HEADER GUARD #ifndef HEAD1_H_ #define HEAD1_H_ // Changed the header file to systemc instead of systemc.h #include<systemc> SC_MODULE(reader) { // sc_fifo_in_if is a abstract class from which you cannot create an object. // sc_fifo_in is derived from the above class which actually implements the read method. sc_core::sc_fifo_in<int> in; void roperation() { int val; while (true) { wait(10, sc_core::SC_NS); // Time unit is defined in sc_core namespace. for (int i = 0; i <= 15; i++) { in.read(val); std::cout << val << std::endl; //< when using the systemc header you need to specify the std namespace. // Or you can use the statement after including all the header files: // using namespace std } } std::cout << "Availaible : " << in.num_available() << std::endl; //< Instead of num available it is num_available //< when using the systemc header you need to specify the std namespace. // Or you can use the statement after including all the header files: // using namespace std } SC_CTOR(reader) //< Your code mentions here writer the constructor name should be same as the class name. { SC_THREAD(roperation); //< Your code mentions woperation } }; #endif // HEAD1_H_  
    //head2.h // Refer the head1.h for similar details #ifndef HEAD2_H_ #define HEAD2_H_ #include<systemc> SC_MODULE(writer) { // Refer the head1.h for similar details sc_core::sc_fifo_out<int> out; void woperation() { int val = 0; while (true) { wait(10, sc_core::SC_NS); for (int i = 0; i <= 20; i++) { out.write(val++); } } } SC_CTOR(writer) { SC_THREAD(woperation); } }; #endif // HEAD2_H_ Here is a minimal makefile for building the example:
    CC=gcc CXX=g++ CXX_FLAGS= -g3 -Wall -c all: main.exe main.exe: main.o ${CXX} $< -o $@ -L${SYSTEMC_HOME}/lib-linux64 -L${SYSTEMC_HOME}/lib -lsystemc main.o: main.cpp head1.h head2.h ${CXX} ${CXX_FLAGS} -I${SYSTEMC_HOME}/include -o $@ $< clean: rm -rf main.o main.exe Note:
    For reference of the sc_fifo_in/out_if classes see here. For more details you can also refer to the SystemC LRM.

    Hope it helps.

    Regards,
    Ameya Vikram Singh
  14. Like
    AmeyaVS reacted to vasu_c in simple test case with SC_THREAD crashes on a debug aarch64 build.   
    Than you Joshua. I missed this update.
    Just applied the patch and it works fine.
    Appreciate the help.
  15. Like
    AmeyaVS reacted to Joshua Landau in simple test case with SC_THREAD crashes on a debug aarch64 build.   
    Hi @vasu_c, thanks for finding this. The patch below should fix your issue if you want to try it out early. Apologies for the inconvenience.
    --- a/src/sysc/packages/qt/md/aarch64.s +++ b/src/sysc/packages/qt/md/aarch64.s @@ -59,8 +59,10 @@ qt_blocki: mov x0, sp // arg0 = old_sp mov sp, x3 // sp = new_sp + sub sp, sp, 160 // (*helper)(old_sp, a0, a1) blr x4 + add sp, sp, 160 // Callee-saved ldp x29, x30, [sp, #-16] // frame, link  
  16. Like
    AmeyaVS got a reaction from veeresh k in Systemc 2.3.2 Changes   
    Hello @sumit_tuwien,
    You can find the necessary details from the SystemC sources.
    You can look into these files for more details:
    RELEASENOTES README NOTICE You can also compare the RELEASENOTES from previous releases.
    Regards,
    Ameya Vikram Singh
  17. Like
    AmeyaVS got a reaction from veeresh k in clock generation in system c   
    Hello @veeresh k,
    This example does not have a dedicated clock generator.
    // These statements are what driving the clock signal to with High time of 1 ns and low time of 1 ns. for (i=0;i<10;i++) { clock = 0; sc_start(1, SC_NS);// Run simulation for 1 ns. clock = 1; sc_start(1, SC_NS);// Run simulation for 1 ns. } What message you receive from the SystemC kernel refers to the timescale of 1 ps e.g.:
    Info: (I702) default timescale unit used for tracing: 1 ps You can get the SystemC API documentation for the sc_clock from here:
    SystemC sc_clock api reference.
    If you need a sample you can find a use-case reference here(though a little bit-dated):
    https://github.com/AmeyaVS/SystemC_ramblings/blob/ff1a111063842bfcd6f5de6bb3db74917dc6331c/src/03_fir/firsytemmain.cpp#L26
    Hope it helps.
    Regards,
    Ameya Vikram Singh
  18. Like
    AmeyaVS reacted to David Black in system c beginner   
    Here is a short list of topics in no particular order you need to be comfortable with in order to be have an easier time learning SystemC:
    [Note: Others might chime in with variations on this list (add/subtract), and this is not necessarily a complete list, but I am fairly certain if you are able to comfortably use the topics I list below, you will have very little trouble syntactically with learning SystemC. In addition to C++, it helps if you have some familiarity with event driven simulation (e.g. SystemVerilog or VHDL). Also, if you have deep knowledge in another OO language (e.g. Java or SystemVerilog), you might have an easier time learning the C++ part.]
    Difference between declaration and definition Pass by value vs pass by reference Use of const (5 distinct cases) Casting C++ style (4 types) Implicit vs explicit conversions Use of function overloading and how to deal with ambiguity issues Use of std::string Use of streaming I/O How to declare, define and use classes Definition of default constructor Purpose and syntax of copy constructor How to declare and use namespaces Operator overloading as member functions and global functions. The difference between overloading and overriding. Relationship between class and struct How to extend classes and multiple inheritance Purpose of public and private Storage types and lifetimes: static, automatic, dynamic How to properly use new and delete Use of pointers and understanding of issues with pointer arithmetic Use of arrays and issues Advantages and use of std::vector<> Use of try-catch and throw Use of initializer list in constructor and a proper understanding of the order of construction Polymorphism and RTTI RAII Rule of 4 (6 if using C++11 or later) How and where to define templates/generic programming (does not need to be deep knowledge - just the basics) Use of templates and nested templates. Definition of full and partial template specialization. Different types of constructors and destructors Use of virtual inheritance (hint: it's not polymorphism) Extra topics:
    More STL including at least std::map<>, std::set<> Boost Modern C++ users (2011 onward) should know about:
    nullptr Uniform initialization Use of auto Use of ranged for Lambda definition, binding and use constexpr std::unique_ptr<>, std::shared_ptr<>
  19. Like
    AmeyaVS got a reaction from David Black in wait in SC_CTOR()   
    Hello @SystemCInDepth,
    The wait() call can only be used in SC_THREAD/SC_CTHREAD registered processes in SystemC library.
    You are trying to call wait even before the elaboration happens and you have started the simulation.
    It would be better if you could go through the book: SystemC from Ground Up by David Black to have a better understanding.
    Hope it helps.
    Regards,
    Ameya Vikram Singh
     
  20. Like
    AmeyaVS got a reaction from ANKUR SAINI in Debugging Multi threaded program in SystemC   
    Hello @ANKUR SAINI,
    If you are on Linux/UNIX with the Accellera release of SystemC library with the GNU toolchain, you can use the following tutorials for reference:
    https://sourceware.org/gdb/onlinedocs/gdb/Threads.html https://stackoverflow.com/questions/1695268/multi-threaded-debugging-tutorial-for-gdb-and-c Due to the co-operative multi-tasking implementation of the SystemC library available from Accellera as @Roman Popov has mentioned, much of the debugging tasks are easier since all threads synchronize with the main library thread.
    Let me know if it helps.
    Regards,
    Ameya Vikram Singh
     
  21. Like
    AmeyaVS got a reaction from swami060 in Debugging Multi threaded program in SystemC   
    Hello @ANKUR SAINI,
    If you are on Linux/UNIX with the Accellera release of SystemC library with the GNU toolchain, you can use the following tutorials for reference:
    https://sourceware.org/gdb/onlinedocs/gdb/Threads.html https://stackoverflow.com/questions/1695268/multi-threaded-debugging-tutorial-for-gdb-and-c Due to the co-operative multi-tasking implementation of the SystemC library available from Accellera as @Roman Popov has mentioned, much of the debugging tasks are easier since all threads synchronize with the main library thread.
    Let me know if it helps.
    Regards,
    Ameya Vikram Singh
     
  22. Like
    AmeyaVS reacted to hle in reset during wait(int)   
    IEEE 1666-2011 describes wait(int ) as follows:
    If my interpretation is correct,
    wait(3); should always be equivalent to
    wait(); wait(); wait(); However, after applying such an equivalent transformation to tests/systemc/kernel/reset_signal_is/test02/test02.cpp from the regression suite, I got a different simulation output (with systemc-2.3.2):
    Is this possibly a bug in the reference implementation?
  23. Like
    AmeyaVS reacted to Philipp A Hartmann in reset during wait(int)   
    I agree with your conclusion that the observed behavior of the proof-of-concept implementation does not match the requirements of IEEE 1666-2011. I checked the code and it can be fixed by adding the check for resets to sc_thread_process.h (in the trigger_static() function):
    diff --git a/src/sysc/kernel/sc_thread_process.h b/src/sysc/kernel/sc_thread_process.h --- a/src/sysc/kernel/sc_thread_process.h +++ b/src/sysc/kernel/sc_thread_process.h @@ -485,5 +486,5 @@ sc_thread_process::trigger_static() #endif // SC_ENABLE_IMMEDIATE_SELF_NOTIFICATIONS - if ( m_wait_cycle_n > 0 ) + if ( m_wait_cycle_n > 0 && THROW_NONE == m_throw_status ) { --m_wait_cycle_n;
    I'll take this change to the language working group to get it fixed in a future version of the SystemC PoC kernel. Thanks for reporting!
    Greetings from Duisburg,
      Philipp
     
  24. Thanks
    AmeyaVS got a reaction from Shashidhar in Clock to Q Propagation Delay   
    Hello,
    In SystemC you can use SC_THREAD's to model delays by using wait statements but you will incur performance penalty.
    Instead you can use event's and event queues to model delays using in SystemC as mentioned here:
    http://workspace.accellera.org/Discussion_Forums/helpforum/archive/msg/msg?list_name=help_forum&monthdir=200803&msg=msg00061.html
    You can replace the SC_THREAD example given in the above mentioned link with SC_METHOD removing the infinite while loop.
    Here's the modified example listed from the above mentioned link:
    template<typename T> class delay_transport : public sc_module { public: sc_in<T> in; sc_out<T> out; SC_HAS_PROCESS(delay_transport); delay_transport(sc_module_name name_, sc_time tdelay_) : sc_module(name_), tdelay(tdelay_), in("in"), out("out") { SC_METHOD(mi); sensitive << in.default_event(); SC_METHOD(mo); sensitive << eq; } sc_time tdelay; void mi() { val = in.read(); vq.push(val); eq.notify(tdelay); } void mo() { val = vq.front(); out.write(val); vq.pop(); } sc_event_queue eq; std::queue<T> vq; T val; }; Regards,
    Ameya Vikram Singh
     
  25. Like
    AmeyaVS got a reaction from maehne in thread resets and events   
    Hello @fdoucet,
    What your are trying to do here in this specific scenario is known as dynamic sensitivity.
    Dynamic sensitivity replaces the default sensitivity of the registered SystemC process, once the event it triggered the default sensitivity would be restored for the corresponding process.
    Here is a reference to the discussion before in this forum:
    http://forums.accellera.org/topic/1210-static-and-dynamic-sensitivity/
    Hope it helps
    Regards,
    Ameya Vikram Singh
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